All some fp instruction documentation

src/simulator/mod.rs

@@ -380,15 +380,43 @@ pub mod global {
     pub const RISCV_FMSUB: u8 = 0x47;
     pub const RISCV_FNMSUB: u8 = 0x4b;
     pub const RISCV_FNMADD: u8 = 0x4f;
+
     /// Simple floating point extension
     pub const RISCV_FP: u8 = 0x53;
 
+    /// Type: R
+    /// 
+    /// Simple precision floating point addition
+    /// 
+    /// `FADD.S rd, rs1, rs2` => `rd <- rs1 + rs2`
     pub const RISCV_FP_ADD: u8 = 0x0;
+    /// Type: R
+    /// 
+    /// Simple precision floating point substraction
+    /// 
+    /// `FSUB.S rd, rs1, rs2` => `rd <- rs1 - rs2`
     pub const RISCV_FP_SUB: u8 = 0x4;
+    /// Type: R
+    /// 
+    /// Simple precision floating point multiplication
+    /// 
+    /// `fmul.s rd, rs1, rs2` => `rd <- rs1 * rs2`
     pub const RISCV_FP_MUL: u8 = 0x8;
+    /// Type : R
+    /// 
+    /// Simple precision floating point division
+    /// 
+    /// `fdiv.s rd, rs1, rs2` => `rd <- rs1 / rs2`
     pub const RISCV_FP_DIV: u8 = 0xc;
+    /// Type: R
+    /// 
+    /// Simple precision square root
+    /// 
+    /// `fsqrt.s rd, rs1` => `rd <- sqrt(rs1)`
     pub const RISCV_FP_SQRT: u8 = 0x2c;
+    /// FSGN instructions
     pub const RISCV_FP_FSGN: u8 = 0x10;
+    // fmin or fmax instructions
     pub const RISCV_FP_MINMAX: u8 = 0x14;
     pub const RISCV_FP_FCVTW: u8 = 0x60;
     pub const RISCV_FP_FMVXFCLASS: u8 = 0x70;
@@ -397,8 +425,23 @@ pub mod global {
     pub const RISCV_FP_FCVTS: u8 = 0x68;
     pub const RISCV_FP_FCVTDS: u8 = 0x21;
 
+    /// Type: R
+    /// 
+    /// Take all bits except sign bit from rs1. sign is rs2's sign bit
+    /// 
+    /// `fsgnj.s rd, rs1, rs2` => `rd <- {rs2[31], rs1[30:0]}`
     pub const RISCV_FP_FSGN_J: u8 = 0x0;
+    /// Type: R
+    /// 
+    /// Take all bits except sign bit from rs1, sign is opposite of rs2's sign bit
+    /// 
+    /// `fsgnjs.s rd, rs1, rs2` => `rd <- {rs2[31], rs[30:0]}`
     pub const RISCV_FP_FSGN_JN: u8 = 0x1;
+    /// Type: R
+    /// 
+    /// Take all bits except sign bit from rs1, sign is XOR of sign bit of rs1 and rs2
+    /// 
+    /// `fsgnjx.s rd, rs1, rs2` => `rd <- {rs1[31] ^ rs2[31], rs1[30:0]}` 
     pub const RISCV_FP_FSGN_JX: u8 = 0x2;
 
     pub const RISCV_FP_MINMAX_MIN: u8 = 0x0;