From 1c6606eb35c7fa7ecb5befc9aae8bf7718612187 Mon Sep 17 00:00:00 2001
From: Baptiste <baptiste.meauze@etudiant.univ-rennes1.fr>
Date: Wed, 1 Feb 2023 17:29:31 +0100
Subject: [PATCH] impl register for floating point (from bottom)

---
 src/simulator/machine.rs | 34 ++++++++++++++++++----------------
 1 file changed, 18 insertions(+), 16 deletions(-)

diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs
index 913abda..3a5fbfa 100644
--- a/src/simulator/machine.rs
+++ b/src/simulator/machine.rs
@@ -59,6 +59,7 @@ impl Register<f32> {
 pub struct Machine {
 	pub pc : u64,
 	pub int_reg : Register<i64>,
+	pub fp_reg : Register<f32>,
 	pub instructions : [u64 ; 100],
 	pub main_memory : [u8 ; MEM_SIZE],
 	pub shiftmask : [u64 ; 64]
@@ -86,6 +87,7 @@ impl Machine {
 			pc : 0,
 			instructions : [0 ; 100],
 			int_reg : Register::<i64>::init(),
+			fp_reg : Register::<f32>::init(),
 			main_memory : [0 ; MEM_SIZE],
 			shiftmask
 		}
@@ -485,10 +487,10 @@ impl Machine {
 								}
 							}
 							RISCV_FP_FSGN_JX => {
-								if (machine.fp_reg[inst.rs2 as usize] < 0 && machine.fp_reg[inst.rs1 as usize] >= 0) || (machine.fp_reg[inst.rs2 as usize] >= 0 && machine.fp_reg[inst.rs1 as usize] < 0) {
-									machine.fp_reg[inst.rd as usize] = -local_float;
+								if (machine.fp_reg.get_reg(inst.rs2 as usize) < 0.0 && machine.fp_reg.get_reg(inst.rs1 as usize) >= 0.0) || (machine.fp_reg.get_reg(inst.rs2 as usize) >= 0.0 && machine.fp_reg.get_reg(inst.rs1 as usize) < 0.0) {
+									machine.fp_reg.set_reg(inst.rd as usize, -local_float);
 								} else {
-									machine.fp_reg[inst.rd as usize] = local_float;
+									machine.fp_reg.set_reg(inst.rd as usize, local_float);
 								}
 							}
 							_ => {
@@ -497,14 +499,14 @@ impl Machine {
 						}
 					},
 					RISCV_FP_MINMAX => {
-						let r1 = machine.fp_reg[inst.rs1 as usize];
-						let r2 = machine.fp_reg[inst.rs2 as usize];
+						let r1 = machine.fp_reg.get_reg(inst.rs1 as usize);
+						let r2 = machine.fp_reg.get_reg(inst.rs2 as usize);
 						match inst.funct3 {
 							RISCV_FP_MINMAX_MIN => {
-								machine.fp_reg[inst.rd as usize] = if r1 < r2 {r1} else {r2}
+								machine.fp_reg.set_reg(inst.rd as usize, if r1 < r2 {r1} else {r2});
 							},
 							RISCV_FP_MINMAX_MAX => {
-								machine.fp_reg[inst.rd as usize] = if r1 > r2 {r1} else {r2}
+								machine.fp_reg.set_reg(inst.rd as usize, if r1 > r2 {r1} else {r2});
 							},
 							_ => {
 								panic!("this instruction ({}) doesn't exists", inst.value);
@@ -513,24 +515,24 @@ impl Machine {
 					},
 					RISCV_FP_FCVTW => {
 						if inst.rs2 == RISCV_FP_FCVTW_W {
-							machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize];
+							machine.int_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) as i64);
 						} else {
-							machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] as u64;
+							machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1 as usize) as u64) as i64);
 						}
 					},
 					RISCV_FP_FCVTS => {
 						if inst.rs2 == RISCV_FP_FCVTS_W {
-							machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize];
+							machine.fp_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) as f32);
 						} else {
-							machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] as u32;
+							machine.fp_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1 as usize) as u32) as f32);
 						}
 					},
 					RISCV_FP_FMVW => {
-						machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize];
+						machine.fp_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) as f32);
 					},
 					RISCV_FP_FMVXFCLASS => {
 						if inst.funct3 == RISCV_FP_FMVXFCLASS_FMVX {
-							machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize];
+							machine.int_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) as i64);
 						} else {
 							panic!("Fclass instruction is not handled in riscv simulator");
 						}
@@ -538,13 +540,13 @@ impl Machine {
 					RISCV_FP_FCMP => {
 						match inst.funct3 {
 							RISCV_FP_FCMP_FEQ => {
-								machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] == machine.fp_reg[inst.rs2 as usize] {1} else {0};
+								machine.int_reg.set_reg(inst.rd as usize, if machine.fp_reg.get_reg(inst.rs1 as usize) == machine.fp_reg.get_reg(inst.rs2 as usize) {1} else {0});
 							},
 							RISCV_FP_FCMP_FLT => {
-								machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] < machine.fp_reg[inst.rs2 as usize] {1} else {0};
+								machine.int_reg.set_reg(inst.rd as usize, if machine.fp_reg.get_reg(inst.rs1 as usize) < machine.fp_reg.get_reg(inst.rs2 as usize) {1} else {0});
 							},
 							RISCV_FP_FCMP_FLE => {
-								machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] <= machine.fp_reg[inst.rs2 as usize] {1} else {0};
+								machine.int_reg.set_reg(inst.rd as usize, if machine.fp_reg.get_reg(inst.rs1 as usize) <= machine.fp_reg.get_reg(inst.rs2 as usize) {1} else {0});
 							},
 							_ => {
 								panic!("this instruction ({}) doesn't exists", inst.value);