From 27cd7d35c7bb73658981f072fe070a02176fb4b7 Mon Sep 17 00:00:00 2001
From: Baptiste <baptiste.meauze@etudiant.univ-rennes1.fr>
Date: Wed, 7 Dec 2022 17:09:53 +0100
Subject: [PATCH] fix ADD_ADD

---
 src/machine.rs | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/src/machine.rs b/src/machine.rs
index b77bd41..2453d23 100644
--- a/src/machine.rs
+++ b/src/machine.rs
@@ -102,8 +102,7 @@ impl Machine {
 
 		let inst : Instruction = decode(machine.instructions[machine.pc as usize]);
 		
-		machine.pc += 4;
-
+		
 		match inst.opcode {
 			RISCV_LUI => {
 				machine.int_reg[inst.rd as usize] = inst.imm31_12 as i64;
@@ -194,6 +193,8 @@ impl Machine {
 				}
 			},
 
+			//TODO store instructions
+
 			//******************************************************************************************
     		// Treatment for: OPI INSTRUCTIONS
 			RISCV_OPI => {
@@ -265,11 +266,11 @@ impl Machine {
 				} else {
 					match inst.funct3 {
 						RISCV_OP_ADD => {
-						// RISCV_OP_ADD_ADD inaccessible
-							/*if (inst.funct7 == RISCV_OP_ADD_ADD) {
-								machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];*/
-							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize];
-							//}
+							if (inst.funct7 == RISCV_OP_ADD_ADD) {
+								machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];
+							} else {
+								machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize];
+							}
 						},
 						RISCV_OP_SLL => {
 							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f);
@@ -371,6 +372,7 @@ impl Machine {
 			_ => { println!("{} opcode non géré", inst.opcode)},
 		}
 
+		machine.pc += 4;
 
 	}
 }