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Merge branch 'decode_print' of gitlab.istic.univ-rennes1.fr:simpleos/burritos into decode_print

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Quentin Legot 2023-02-01 17:32:19 +01:00
commit 4302b9ce23
1 changed files with 17 additions and 17 deletions
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32
src/simulator/machine.rs
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@ -487,10 +487,10 @@ impl Machine {
}
}
RISCV_FP_FSGN_JX => {
if (machine.fp_reg[inst.rs2 as usize] < 0 && machine.fp_reg[inst.rs1 as usize] >= 0) || (machine.fp_reg[inst.rs2 as usize] >= 0 && machine.fp_reg[inst.rs1 as usize] < 0) {
machine.fp_reg[inst.rd as usize] = -local_float;
if (machine.fp_reg.get_reg(inst.rs2 as usize) < 0.0 && machine.fp_reg.get_reg(inst.rs1 as usize) >= 0.0) || (machine.fp_reg.get_reg(inst.rs2 as usize) >= 0.0 && machine.fp_reg.get_reg(inst.rs1 as usize) < 0.0) {
machine.fp_reg.set_reg(inst.rd as usize, -local_float);
} else {
machine.fp_reg[inst.rd as usize] = local_float;
machine.fp_reg.set_reg(inst.rd as usize, local_float);
}
}
_ => {
@ -499,14 +499,14 @@ impl Machine {
}
},
RISCV_FP_MINMAX => {
let r1 = machine.fp_reg[inst.rs1 as usize];
let r2 = machine.fp_reg[inst.rs2 as usize];
let r1 = machine.fp_reg.get_reg(inst.rs1 as usize);
let r2 = machine.fp_reg.get_reg(inst.rs2 as usize);
match inst.funct3 {
RISCV_FP_MINMAX_MIN => {
machine.fp_reg[inst.rd as usize] = if r1 < r2 {r1} else {r2}
machine.fp_reg.set_reg(inst.rd as usize, if r1 < r2 {r1} else {r2});
},
RISCV_FP_MINMAX_MAX => {
machine.fp_reg[inst.rd as usize] = if r1 > r2 {r1} else {r2}
machine.fp_reg.set_reg(inst.rd as usize, if r1 > r2 {r1} else {r2});
},
_ => {
panic!("this instruction ({}) doesn't exists", inst.value);
@ -515,24 +515,24 @@ impl Machine {
},
RISCV_FP_FCVTW => {
if inst.rs2 == RISCV_FP_FCVTW_W {
machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize];
machine.int_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) as i64);
} else {
machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] as u64;
machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1 as usize) as u64) as i64);
}
},
RISCV_FP_FCVTS => {
if inst.rs2 == RISCV_FP_FCVTS_W {
machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize];
machine.fp_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) as f32);
} else {
machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] as u32;
machine.fp_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1 as usize) as u32) as f32);
}
},
RISCV_FP_FMVW => {
machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize];
machine.fp_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) as f32);
},
RISCV_FP_FMVXFCLASS => {
if inst.funct3 == RISCV_FP_FMVXFCLASS_FMVX {
machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize];
machine.int_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) as i64);
} else {
panic!("Fclass instruction is not handled in riscv simulator");
}
@ -540,13 +540,13 @@ impl Machine {
RISCV_FP_FCMP => {
match inst.funct3 {
RISCV_FP_FCMP_FEQ => {
machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] == machine.fp_reg[inst.rs2 as usize] {1} else {0};
machine.int_reg.set_reg(inst.rd as usize, if machine.fp_reg.get_reg(inst.rs1 as usize) == machine.fp_reg.get_reg(inst.rs2 as usize) {1} else {0});
},
RISCV_FP_FCMP_FLT => {
machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] < machine.fp_reg[inst.rs2 as usize] {1} else {0};
machine.int_reg.set_reg(inst.rd as usize, if machine.fp_reg.get_reg(inst.rs1 as usize) < machine.fp_reg.get_reg(inst.rs2 as usize) {1} else {0});
},
RISCV_FP_FCMP_FLE => {
machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] <= machine.fp_reg[inst.rs2 as usize] {1} else {0};
machine.int_reg.set_reg(inst.rd as usize, if machine.fp_reg.get_reg(inst.rs1 as usize) <= machine.fp_reg.get_reg(inst.rs2 as usize) {1} else {0});
},
_ => {
panic!("this instruction ({}) doesn't exists", inst.value);