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Removed wrong spaces

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This commit is contained in:
Samy Solhi 2023-02-07 22:05:35 +01:00
parent 89aaa4e821
commit 4438218d33
1 changed files with 20 additions and 20 deletions
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40
src/simulator/print.rs
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@ -51,15 +51,15 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
} else {
name = NAMES_OP[ins.funct3 as usize];
}
format!("{}\t{}, {}, {}", name, REG_X[rd], REG_X[rs1], REG_X[rs2])
format!("{}\t{},{},{}", name, REG_X[rd], REG_X[rs1], REG_X[rs2])
},
RISCV_OPI => {
// SHAMT OR IMM
if ins.funct3 == RISCV_OPI_SRI {
if ins.funct7 == RISCV_OPI_SRI_SRLI {
format!("srli\t{}, {}, {}", REG_X[rd], REG_X[rs1], ins.shamt)
format!("srli\t{},{},{}", REG_X[rd], REG_X[rs1], ins.shamt)
} else {
format!("srai\t{}, {}, {}", REG_X[rd], REG_X[rs1], ins.shamt)
format!("srai\t{},{},{}", REG_X[rd], REG_X[rs1], ins.shamt)
}
} else if ins.funct3 == RISCV_OPI_SLLI {
format!("{}\t{},{},{}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.shamt)
@ -68,10 +68,10 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
}
},
RISCV_LUI => {
format!("lui\t{}, 0x{:x}", REG_X[rd], ins.imm31_12)
format!("lui\t{},{:x}", REG_X[rd], ins.imm31_12)
},
RISCV_AUIPC => {
format!("auipc\t{}, {:x}", REG_X[rd], ins.imm31_12)
format!("auipc\t{},{:x}", REG_X[rd], ins.imm31_12)
},
RISCV_JAL => {
format!("jal\t{},{:x}", REG_X[rd], (pc + ins.imm21_1_signed))
@ -91,19 +91,19 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
RISCV_OPIW => {
if ins.funct3 == RISCV_OPIW_SRW {
if ins.funct7 == RISCV_OPIW_SRW_SRLIW {
format!("srliw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2])
format!("srliw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2])
} else {
format!("sraiw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2])
format!("sraiw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2])
}
} else if ins.funct3 == RISCV_OPIW_SLLIW {
format!("{}\t{}, {}, {}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2])
format!("{}\t{},{},{}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2])
} else {
format!("{}\t{}, {}, {}", NAMES_OPIW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed)
format!("{}\t{},{},{}", NAMES_OPIW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed)
}
},
RISCV_OPW => {
if ins.funct7 == 1 {
format!("{}w\t{}, {}, {}", NAMES_MUL[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2])
format!("{}w\t{},{},{}", NAMES_MUL[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2])
} else if ins.funct3 == RISCV_OP_ADD {
if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW {
format!("addw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2])
@ -144,11 +144,11 @@ mod test {
let slr = decode::decode(0b0000000_10000_10001_101_11100_0110011);
let sra = decode::decode(0b0100000_10000_10001_101_11100_0110011);
assert_eq!("sub\tt3, a7, a6", print::print(sub, 0));
assert_eq!("xor\tt3, a7, a6", print::print(xor, 0));
assert_eq!("srl\tt3, a7, a6", print::print(slr, 0));
assert_eq!("sra\tt3, a7, a6", print::print(sra, 0));
assert_eq!("add\tt3, a7, a6", print::print(add, 0));
assert_eq!("sub\tt3,a7,a6", print::print(sub, 0));
assert_eq!("xor\tt3,a7,a6", print::print(xor, 0));
assert_eq!("srl\tt3,a7,a6", print::print(slr, 0));
assert_eq!("sra\tt3,a7,a6", print::print(sra, 0));
assert_eq!("add\tt3,a7,a6", print::print(add, 0));
}
@ -174,8 +174,8 @@ mod test {
fn test_lui() {
let lui = decode::decode(0b01110001000011111000_11100_0110111);
let lui_negatif = decode::decode(0b11110001000011111000_11100_0110111);
assert_eq!("lui\tt3, 0x710f8000", print::print(lui, 0));
assert_eq!("lui\tt3, 0xf10f8000", print::print(lui_negatif, 0));
assert_eq!("lui\tt3,710f8000", print::print(lui, 0));
assert_eq!("lui\tt3,f10f8000", print::print(lui_negatif, 0));
}
#[test]
@ -216,9 +216,9 @@ mod test {
let addiw: decode::Instruction =decode::decode(0b000000000000_10001_000_11100_0011011);
let slliw: decode::Instruction = decode::decode(0b0000000_10000_10001_001_11100_0011011);
let srai: decode::Instruction = decode::decode(0b010000010001_10001_101_11100_0010011);
assert_eq!("addiw\tt3, a7, 0", print::print(addiw, 0));
assert_eq!("slli\tt3, a7, a6", print::print(slliw, 0));
assert_eq!("srai\tt3, a7, 17", print::print(srai, 0));
assert_eq!("addiw\tt3,a7,0", print::print(addiw, 0));
assert_eq!("slli\tt3,a7,a6", print::print(slliw, 0));
assert_eq!("srai\tt3,a7,17", print::print(srai, 0));
}