LOAD and BRANCH instructions

src/machine.rs

@@ -6,7 +6,7 @@ const MEM_SIZE : usize= 4096;
 
 pub struct Machine {
 	pub pc : u64,
-	pub int_reg : [u64 ; 32],
+	pub int_reg : [i64 ; 32],
 	pub instructions : [u64 ; 100],
 	pub main_memory : [u8 ; MEM_SIZE],
 	pub shiftmask : [u64 ; 64]
@@ -36,6 +36,33 @@ impl Machine {
 		}	
 	}
 
+	/// Read from main memory of the machine
+	///
+	/// ### Parameters
+	///
+	/// - **machine** which contains the main memory
+	/// - **size** the number of bytes to read (1, 2, 4, 8)
+	/// - **address** in the memory to read
+	pub fn read_memory(machine : &mut Machine, size : i32, address : usize) -> u64 {
+		if size != 1 && size != 2 && size != 4 && size != 8 {
+			println!("ERROR read_memory : wrong size parameter {}, must be (1, 2, 4 or 8)", size);
+		}
+
+		let mut ret : u64 = machine.main_memory[address] as u64;
+		if size == 2 || size == 4 || size == 8 {
+			ret = ret << 8;
+			ret += machine.main_memory[address + 1] as u64;
+		}
+		if size == 4 || size == 8 {
+			ret = ret << 8;
+			ret += machine.main_memory[address + 2] as u64;
+		}
+		if size == 8 {
+			ret = ret << 8;
+			ret += machine.main_memory[address + 3] as u64;
+		}
+		return ret;
+	}
 
 	/// Execute the instructions table of a machine putted in param
 	/// 
@@ -79,46 +106,120 @@ impl Machine {
 
 		match inst.opcode {
 			RISCV_LUI => {
-				machine.int_reg[inst.rd as usize] = inst.imm31_12 as u64;
+				machine.int_reg[inst.rd as usize] = inst.imm31_12 as i64;
 			},
 			RISCV_AUIPC => {
-				machine.int_reg[inst.rd as usize] = machine.pc - 4 + inst.imm31_12 as u64;
+				machine.int_reg[inst.rd as usize] = machine.pc as i64 - 4 + inst.imm31_12 as i64;
 			},
 			RISCV_JAL => {
-				machine.int_reg[inst.rd as usize] = machine.pc;
+				machine.int_reg[inst.rd as usize] = machine.pc as i64;
 				machine.pc += inst.imm21_1_signed as u64 - 4;
 			},
 			RISCV_JALR => {
 				let tmp = machine.pc;
-				machine.pc = (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as u64) & 0xfffffffe;
+				machine.pc = (machine.int_reg[inst.rs1 as usize] as u64 + inst.imm12_I_signed as u64) & 0xfffffffe;
-				machine.int_reg[inst.rd as usize] = tmp;
+				machine.int_reg[inst.rd as usize] = tmp as i64;
-			}
+			},
+
+			//******************************************************************************************
+  			// Treatment for: BRANCH INSTRUCTIONS
+			RISCV_BR => {
+				match inst.funct3 {
+					RISCV_BR_BEQ => {
+						if machine.int_reg[inst.rs1 as usize] == machine.int_reg[inst.rs2 as usize] {
+							machine.pc += inst.imm13_signed as u64 - 4;
+						}
+					},
+					RISCV_BR_BNE => {
+						if machine.int_reg[inst.rs1 as usize] != machine.int_reg[inst.rs2 as usize] {
+							machine.pc += inst.imm13_signed as u64 - 4;
+						}
+					},
+					RICV_BR_BLT => {
+						if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
+							machine.pc += inst.imm13_signed as u64 - 4;
+						}
+					},
+					RICV_BR_BGE => {
+						if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] {
+							machine.pc += inst.imm13_signed as u64 - 4;
+						}
+					},
+					RICV_BR_BLTU => {
+						if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
+							machine.pc += inst.imm13_signed as u64 - 4;
+						}
+					},
+					RICV_BR_BGEU => {
+						if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] {
+							machine.pc += inst.imm13_signed as u64 - 4;
+						}
+					},
+					_ => {
+						println!("In BR switch case, this should never happen... Instr was {}", inst.value);
+					}
+				}
+			},
+
+			//******************************************************************************************
+    		// Treatment for: LOAD INSTRUCTIONS
+			RISCV_LD => {
+				match inst.funct3 {
+					RISCV_LD_LB => {
+						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
+					},
+					RISCV_LD_LH => {
+						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
+					},
+					RISCV_LD_LW => {
+						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
+					},
+					RISCV_LD_LD => {
+						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 8, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
+					},
+
+					// same thing three opration ? 
+					RISCV_LD_LBU => {
+						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
+					},
+					RISCV_LD_LHU => {
+						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
+					},
+					RISCV_LD_LWU => {
+						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
+					},
+					_ => {
+						println!("In LD switch case, this should never happen... Instr was {}", inst.value);
+					}
+				}
+			},
+
 			//******************************************************************************************
     		// Treatment for: OPI INSTRUCTIONS
 			RISCV_OPI => {
 				match inst.funct3 {
 					RISCV_OPI_ADDI => {
-						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as u64;
+						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64;
 					},
 					RISCV_OPI_SLTI => {
 						machine.int_reg[inst.rd as usize] = 
-							if machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as u64 { 1 } else { 0 };
+							if machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as i64 { 1 } else { 0 };
 					},
 					RISCV_OPI_XORI => {
-						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as u64;
+						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as i64;
 					},
 					RISCV_OPI_ORI => {
-						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | inst.imm12_I_signed as u64;
+						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | inst.imm12_I_signed as i64;
 					},
 					RISCV_OPI_ANDI => {
-						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & inst.imm12_I_signed as u64;
+						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & inst.imm12_I_signed as i64;
 					},
 					RISCV_OPI_SLLI => {
 						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt;
 					},
 					RISCV_OPI_SRI => {
 						if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {
-							machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt) & machine.shiftmask[inst.shamt as usize];
+							machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64;
 						} else { // SRAI
 							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> inst.shamt;	
 						}
@@ -127,17 +228,12 @@ impl Machine {
 				}
 			},
 			
-			RISCV_JAL => {
-				machine.int_reg[inst.rd as usize] = machine.pc;
-				machine.pc = machine.pc - 4 + (inst.imm21_1_signed as u64);
-			},
-			
 			RISCV_OP => {
 				if inst.funct7 == 1{
 					match inst.funct3 {
 						RISCV_OP_M_MUL => {
 							long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128;
-							machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as u64;
+							machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as i64;
 						},
 						RISCV_OP_M_MULH => {
 							long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128;
@@ -146,7 +242,7 @@ impl Machine {
 						RISCV_OP_M_MULHSU => {
 							unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
             						long_result   = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128;
-            						machine.int_reg[inst.rd as usize]    = ((long_result >> 64) & 0xffffffffffffffff) as u64;
+            						machine.int_reg[inst.rd as usize]    = ((long_result >> 64) & 0xffffffffffffffff) as i64;
 						},
 						// VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve
 						/*
@@ -157,7 +253,7 @@ impl Machine {
 							unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
             						unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
             						long_result   = (unsigned_reg1 * unsigned_reg2) as i128;
-	   						machine.int_reg[inst.rd as usize]    = ((long_result >> 64) & 0xffffffffffffffff) as u64;
+	   						machine.int_reg[inst.rd as usize]    = ((long_result >> 64) & 0xffffffffffffffff) as i64;
 						},
 						RISCV_OP_M_DIV => {
 							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize];
@@ -261,7 +357,7 @@ impl Machine {
 						},
 						RISCV_OPW_SRW => {
 							if inst.funct7 == RISCV_OPW_SRW_SRLW {
-								machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize];
+								machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize] as i64;
 							} else { // SRAW
 								machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f);
 							}

src/main.rs

@@ -5,6 +5,11 @@ use machine::Machine;
 
 fn main() {
     let mut m = Machine::_init_machine();
-    m.instructions[0] = 0x37;
+    m.main_memory[4] = 43;
-    Machine::one_instruction(&mut m);
+    m.main_memory[5] = 150;
+    let a : u8 = 128;
+    let b : i8 = a as i8;
+    let c : u8 = b as u8;
+    println!("aaa {}", c);
+    println!("read_memory : {}", Machine::read_memory(&mut m, 2, 4));
 }