From 547abd001b7b4900b55b54c55ac6c9417bcbbc4c Mon Sep 17 00:00:00 2001
From: Quentin Legot <legotquentin@gmail.com>
Date: Mon, 16 Jan 2023 19:12:20 +0100
Subject: [PATCH] Update some println to panic, fix RISCV_OP_M_MULH (line 270),
 add write_memory structure

---
 src/simulator/machine.rs | 57 +++++++++++++++++++++++++++++++---------
 1 file changed, 44 insertions(+), 13 deletions(-)

diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs
index a8084eb..672db4e 100644
--- a/src/simulator/machine.rs
+++ b/src/simulator/machine.rs
@@ -63,6 +63,19 @@ impl Machine {
 		ret
 	}
 
+	/// Write to the main memory of the machine
+	/// 
+	/// **machine** contains the memory
+	/// **size** the number of bytes to write (1, 2, 4 or 8)
+	/// **address** the address to write to
+	/// **value** data to be written
+	pub fn write_memory(machine: &mut Machine, size: i32, address: usize, value: i64) {
+		if ![1, 2, 3, 4].contains(&size) {
+			panic!("ERROR write_memory: WRONG `size` PARAMETER ({}), must be 1, 2, 4 or 8", size)
+		}
+		todo!("Write memory not implemented yet");
+	}
+
 	/// Execute the instructions table of a machine putted in param
 	/// 
 	/// ### Parameters
@@ -154,7 +167,7 @@ impl Machine {
 						}
 					},
 					_ => {
-						println!("In BR switch case, this should never happen... Instr was {}", inst.value);
+						panic!("In BR switch case, this should never happen... Instr was {}", inst.value);
 					}
 				}
 			},
@@ -187,13 +200,31 @@ impl Machine {
 						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
 					},
 					_ => {
-						println!("In LD switch case, this should never happen... Instr was {}", inst.value);
+						panic!("In LD switch case, this should never happen... Instr was {}", inst.value);
 					}
 				}
 			},
 
 			//TODO store instructions
-
+			RISCV_ST => {
+				match inst.funct3 {
+					RISCV_ST_STB => {
+						todo!("Write memory here");
+					},
+					RISCV_ST_STH => {
+						todo!("Write memory here");
+					},
+					RISCV_ST_STW => {
+						todo!("Write memory here");
+					},
+					RISCV_ST_STD => {
+						todo!("Write memory here");
+					},
+					_ => {
+						panic!("In ST switch case, this should never happen... Instr was {}", inst.value);
+					}
+				}
+			}
 			//******************************************************************************************
     		// Treatment for: OPI INSTRUCTIONS
 			RISCV_OPI => {
@@ -223,12 +254,12 @@ impl Machine {
 							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> inst.shamt;	
 						}
 					}
-					_ => { println!("{} inconnu", inst.funct3); }
+					_ => { panic!("{} inconnu", inst.funct3); }
 				}
 			},
 			
 			RISCV_OP => {
-				if inst.funct7 == 1{
+				if inst.funct7 == 1 {
 					match inst.funct3 {
 						RISCV_OP_M_MUL => {
 							long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128;
@@ -236,12 +267,12 @@ impl Machine {
 						},
 						RISCV_OP_M_MULH => {
 							long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128;
-												
+							machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64;
 						},
 						RISCV_OP_M_MULHSU => {
 							unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
-            						long_result   = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128;
-            						machine.int_reg[inst.rd as usize]    = ((long_result >> 64) & 0xffffffffffffffff) as i64;
+            				long_result   = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128;
+            				machine.int_reg[inst.rd as usize]    = ((long_result >> 64) & 0xffffffffffffffff) as i64;
 						},
 						// VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve
 						/*
@@ -258,7 +289,7 @@ impl Machine {
 							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize];
 						}
 						_ => {
-							println!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n");
+							panic!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n");
 						}
 					}
 				} else {
@@ -303,7 +334,7 @@ impl Machine {
 							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize];
 						},
 						_ => {
-							println!("RISCV_OP undefined case\n");
+							panic!("RISCV_OP undefined case\n");
 						}
 					}//LA
 				}
@@ -335,7 +366,7 @@ impl Machine {
 							machine.int_reg[inst.rd as usize] = local_data_a_unsigned % local_data_b_unsigned;
 						},
 						_ => {
-							println!("this instruction ({}) doesn't exists", inst.value);
+							panic!("this instruction ({}) doesn't exists", inst.value);
 						}
 					}
 				} else {
@@ -362,12 +393,12 @@ impl Machine {
 							}
 						},
 						_ => {
-							println!("this instruction ({}) doesn't exists", inst.value);
+							panic!("this instruction ({}) doesn't exists", inst.value);
 						}
 					}
 				}
 			}
-			_ => { println!("{} opcode non géré", inst.opcode)},
+			_ => { panic!("{} opcode non géré", inst.opcode)},
 		}
 
 		machine.pc += 4;