🚨 Cleaned up clippy warnings for machine.rs
This commit is contained in:
parent
fe2fe40a75
commit
5c37563322
@ -23,7 +23,7 @@ impl Machine {
|
|||||||
value = (value << 32) + value;
|
value = (value << 32) + value;
|
||||||
for item in &mut shiftmask {
|
for item in &mut shiftmask {
|
||||||
*item = value;
|
*item = value;
|
||||||
value = value >> 1;
|
value >>= 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
Machine {
|
Machine {
|
||||||
@ -202,8 +202,7 @@ impl Machine {
|
|||||||
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64;
|
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64;
|
||||||
},
|
},
|
||||||
RISCV_OPI_SLTI => {
|
RISCV_OPI_SLTI => {
|
||||||
machine.int_reg[inst.rd as usize] =
|
machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as i64) as i64;
|
||||||
if machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as i64 { 1 } else { 0 };
|
|
||||||
},
|
},
|
||||||
RISCV_OPI_XORI => {
|
RISCV_OPI_XORI => {
|
||||||
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as i64;
|
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as i64;
|
||||||
@ -378,6 +377,5 @@ impl Machine {
|
|||||||
|
|
||||||
#[cfg(test)]
|
#[cfg(test)]
|
||||||
mod test {
|
mod test {
|
||||||
use super::Machine;
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
Loading…
Reference in New Issue
Block a user