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📝 :refactor: Form and documentation updates

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This commit is contained in:
François Autin 2023-03-25 15:37:14 +01:00
parent 7ed53261a0
commit 651e03a446
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GPG Key ID: 343F5D382E1DD77C
1 changed files with 34 additions and 34 deletions
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64
src/simulator/machine.rs
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@ -94,19 +94,16 @@ impl Machine {
value >>= 1; value >>= 1;
} }
let mut ret = Machine { Machine {
pc : 0, pc : 0,
sp: 0, sp: 0,
int_reg : Register::<i64>::init(), int_reg : { let mut r = Register::<i64>::init(); r.set_reg(10, -1); r },
fp_reg : Register::<f32>::init(), fp_reg : Register::<f32>::init(),
main_memory : vec![0_u8; MEM_SIZE], main_memory : vec![0_u8; MEM_SIZE],
shiftmask, shiftmask,
interrupt: Interrupt::new(), interrupt: Interrupt::new(),
registers_trace : String::from("") registers_trace : String::from("")
}; }
ret.int_reg.set_reg(10, -1);
ret
} }
/// Read from main memory of the machine /// Read from main memory of the machine
@ -242,58 +239,61 @@ impl Machine {
self.pc += 4; self.pc += 4;
match inst.opcode { match inst.opcode {
// Treatment for: LOAD UPPER IMMEDIATE INSTRUCTION
RISCV_LUI => { RISCV_LUI => {
self.int_reg.set_reg(inst.rd, inst.imm31_12 as i64); self.int_reg.set_reg(inst.rd, inst.imm31_12 as i64);
Ok(()) Ok(())
}, },
// Treatment for: ADD UPPER IMMEDIATE TO PC INSTRUCTION
RISCV_AUIPC => { RISCV_AUIPC => {
self.int_reg.set_reg(inst.rd, self.pc as i64 - 4 + inst.imm31_12 as i64); self.int_reg.set_reg(inst.rd, self.pc as i64 - 4 + inst.imm31_12 as i64);
Ok(()) Ok(())
}, },
// Treatement for: JUMP AND LINK INSTRUCTIONS (direct jump)
RISCV_JAL => { RISCV_JAL => {
self.int_reg.set_reg(inst.rd, self.pc as i64); self.int_reg.set_reg(inst.rd, self.pc as i64);
self.pc = (self.pc as i64 + inst.imm21_1_signed as i64 - 4) as u64; self.pc = (self.pc as i64 + inst.imm21_1_signed as i64 - 4) as u64;
Ok(()) Ok(())
}, },
// Treatment for: JUMP AND LINK REGISTER INSTRUCTIONS (indirect jump)
RISCV_JALR => { RISCV_JALR => {
let tmp = self.pc; let tmp = self.pc;
self.pc = (self.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64) as u64 & 0xfffffffe; self.pc = (self.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64) as u64 & 0xfffffffe;
self.int_reg.set_reg(inst.rd, tmp as i64); self.int_reg.set_reg(inst.rd, tmp as i64);
Ok(()) Ok(())
}, },
// Treatment for: BRANCH INSTRUCTIONS // Treatment for: BRANCH INSTRUCTIONS
RISCV_BR => { RISCV_BR => self.branch_instruction(inst),
self.branch_instruction(inst)
},
// Treatment for: LOAD INSTRUCTIONS // Treatment for: LOAD INSTRUCTIONS
RISCV_LD => { RISCV_LD => self.load_instruction(inst),
self.load_instruction(inst)
}, // Treatment for: STORE INSTRUCTIONS
// store instructions RISCV_ST => self.store_instruction(inst),
RISCV_ST => {
self.store_instruction(inst)
},
// Treatment for: OPI INSTRUCTIONS // Treatment for: OPI INSTRUCTIONS
RISCV_OPI => { RISCV_OPI => self.opi_instruction(inst),
self.opi_instruction(inst)
}, // Treatment for: OP INSTRUCTIONS
RISCV_OP => { RISCV_OP => self.op_instruction(inst),
self.op_instruction(inst)
},
// Treatment for OPIW INSTRUCTIONS // Treatment for OPIW INSTRUCTIONS
RISCV_OPIW => { RISCV_OPIW => self.opiw_instruction(inst),
self.opiw_instruction(inst)
},
// Treatment for: OPW INSTRUCTIONS // Treatment for: OPW INSTRUCTIONS
RISCV_OPW => self.opw_instruction(inst), RISCV_OPW => self.opw_instruction(inst),
// Treatment for: Simple floating point extension
// Treatment for: FLOATING POINT INSTRUCTIONS
RISCV_FP => self.fp_instruction(inst), RISCV_FP => self.fp_instruction(inst),
// Treatment for: System instructions
RISCV_SYSTEM => { // Treatment for: SYSTEM CALLS
// temporary return value to stop the loop of run RISCV_SYSTEM => Err(MachineError::new(format!("{:x}: System opcode\npc: {:x}", inst.opcode, self.pc).as_str())),
// before we can use system call
Err(MachineError::new(format!("{:x}: System opcode\npc: {:x}", inst.opcode, self.pc).as_str())) // Default case
},
_ => Err(MachineError::new(format!("{:x}: Unknown opcode\npc: {:x}", inst.opcode, self.pc).as_str())) _ => Err(MachineError::new(format!("{:x}: Unknown opcode\npc: {:x}", inst.opcode, self.pc).as_str()))
} }
} }