From 67ebff7ad06ae88d49246f704dd25330e615fa6b Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 1 Feb 2023 17:04:10 +0100 Subject: [PATCH] Update registers access on RISCV_OP --- src/simulator/machine.rs | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 45bafe7..d27dc60 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -295,9 +295,9 @@ impl Machine { }, RISCV_OPI_SRI => { if inst.funct7_smaller == RISCV_OPI_SRI_SRLI { - machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64; + machine.int_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1 as usize) >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64); } else { // SRAI - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> inst.shamt; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) >> inst.shamt); } } _ => { panic!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value); } @@ -308,17 +308,17 @@ impl Machine { if inst.funct7 == 1 { match inst.funct3 { RISCV_OP_M_MUL => { - long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; - machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as i64; + long_result = (machine.int_reg.get_reg(inst.rs1 as usize) * machine.int_reg.get_reg(inst.rs2 as usize)) as i128; + machine.int_reg.set_reg(inst.rd as usize, (long_result & 0xffffffffffffffff) as i64); }, RISCV_OP_M_MULH => { - long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; - machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; + long_result = (machine.int_reg.get_reg(inst.rs1 as usize) * machine.int_reg.get_reg(inst.rs2 as usize)) as i128; + machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64); }, RISCV_OP_M_MULHSU => { - unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; - long_result = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128; - machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; + unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64; + long_result = (machine.int_reg.get_reg(inst.rs1 as usize) as u64 * unsigned_reg2) as i128; + machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64); }, // VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve /* @@ -326,13 +326,13 @@ impl Machine { * WHAT DA HECK */ RISCV_OP_M_MULHU => { - unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64; - unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; + unsigned_reg1 = machine.int_reg.get_reg(inst.rs1 as usize) as u64; + unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64; long_result = (unsigned_reg1 * unsigned_reg2) as i128; - machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; + machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64); }, RISCV_OP_M_DIV => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize]; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) / machine.int_reg.get_reg(inst.rs2 as usize)); } _ => { panic!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n");