memory.txt can be execute
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@ -8,7 +8,7 @@ fn main() {
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let path = "memory.txt".to_string();
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let checker = mem_cmp::Mem_Checker::from(&path);
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mem_cmp::Mem_Checker::fill_memory_from_Mem_Checker(&checker, &mut m);
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mem_cmp::Mem_Checker::print_Mem_Checker(&checker);
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Machine::print_memory(&mut m, 0x400000, 0x405000);
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//mem_cmp::Mem_Checker::print_Mem_Checker(&checker);
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//Machine::print_memory(&mut m, 0x400000, 0x405000);
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Machine::run(m);
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}
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@ -1,5 +1,7 @@
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use std::{ops::{Add, Sub}, io::Write};
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use crate::simulator::print;
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use super::{decode::{Instruction, decode}};
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use super::global::*;
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use std::fs::File;
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@ -40,7 +42,7 @@ impl Register<i64> {
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self.register[position] = value;
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} else {
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// Panic ou rien ? (dans le doute pour le moment panic)
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unreachable!("You can't write to zero register")
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// unreachable!("You can't write to zero register")
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}
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}
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@ -148,6 +150,14 @@ impl Machine {
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file.write(&machine.main_memory);
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}
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pub fn print_machine_status(machine: &mut Machine) {
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println!("######### Machine status #########");
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for i in 0..32 {
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println!(">{} : {:x}", print::REG_X[i], machine.int_reg.get_reg(i));
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}
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println!("##################################");
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}
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/// Execute the instructions table of a machine putted in param
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///
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/// ### Parameters
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@ -182,13 +192,15 @@ impl Machine {
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if machine.main_memory.len() <= machine.pc as usize {
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panic!("ERROR : number max of instructions rushed");
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}
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let mut val: [u8; 8] = [0; 8];
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for i in 0..8 {
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let mut val: [u8; 4] = [0; 4];
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for i in 0..4 {
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val[i] = machine.main_memory[machine.pc as usize + i];
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}
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let val = u64::from_be_bytes(val);
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println!("{:x}", val);
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let val = u32::from_be_bytes(val) as u64;
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Self::print_machine_status(machine);
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println!("executing instruction : {:016x} at pc {:x}", val, machine.pc);
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println!("{}", print::print(decode(val), machine.pc as i32));
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let inst : Instruction = decode(val);
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@ -160,6 +160,7 @@ impl Mem_Checker{
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pub fn fill_memory_from_Mem_Checker(m_c: &Mem_Checker, machine: &mut Machine){
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machine.sp = m_c.sp;
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machine.int_reg.set_reg(2, m_c.pc as i64);
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machine.pc = m_c.pc as u64;
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@ -13,7 +13,7 @@ const NAMES_OPIW: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""];
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// Register name mapping
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const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1",
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pub const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1",
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"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
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"s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
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"t3", "t4", "t5", "t6"];
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@ -78,7 +78,7 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
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format!("jal\t{},{:x}", REG_X[rd], (pc + ins.imm21_1_signed))
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},
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RISCV_JALR => {
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format!("jalr\t{},{}({})", REG_X[rd], ins.imm12_I_signed, REG_X[rs1])
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format!("jalr\t{},{:x}({})", REG_X[rd], ins.imm12_I_signed, REG_X[rs1])
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},
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RISCV_BR => {
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format!("{}\t{},{},{:x}", NAMES_BR[ins.funct3 as usize], REG_X[rs1], REG_X[rs2], pc + (ins.imm13_signed as i32))
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