From 7bdde709895cec79e0d19a3fb4b3c3d34de4aa29 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Fri, 24 Mar 2023 18:20:59 +0100 Subject: [PATCH] :recycle: Removed tons of casts to usize --- src/simulator/machine.rs | 138 +++++++++++++++++++------------------- src/simulator/register.rs | 4 +- 2 files changed, 71 insertions(+), 71 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 6b5e64b..c9c1877 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -230,22 +230,22 @@ impl Machine { match inst.opcode { RISCV_LUI => { - machine.int_reg.set_reg(inst.rd as usize, inst.imm31_12 as i64); + machine.int_reg.set_reg(inst.rd, inst.imm31_12 as i64); Ok(()) }, RISCV_AUIPC => { - machine.int_reg.set_reg(inst.rd as usize,machine.pc as i64 - 4 + inst.imm31_12 as i64); + machine.int_reg.set_reg(inst.rd,machine.pc as i64 - 4 + inst.imm31_12 as i64); Ok(()) }, RISCV_JAL => { - machine.int_reg.set_reg(inst.rd as usize, machine.pc as i64); + machine.int_reg.set_reg(inst.rd, machine.pc as i64); machine.pc = (machine.pc as i64 + inst.imm21_1_signed as i64 - 4) as u64; Ok(()) }, RISCV_JALR => { let tmp = machine.pc; machine.pc = (machine.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64) as u64 & 0xfffffffe; - machine.int_reg.set_reg(inst.rd as usize, tmp as i64); + machine.int_reg.set_reg(inst.rd, tmp as i64); Ok(()) }, // Treatment for: BRANCH INSTRUCTIONS @@ -330,19 +330,19 @@ impl Machine { match inst.funct3 { RISCV_LD_LB | RISCV_LD_LBU => { let tmp = Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64) as usize) as i64; - machine.int_reg.set_reg(inst.rd as usize, tmp); + machine.int_reg.set_reg(inst.rd, tmp); }, RISCV_LD_LH | RISCV_LD_LHU => { let tmp = Self::read_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64) as usize) as i64; - machine.int_reg.set_reg(inst.rd as usize, tmp); + machine.int_reg.set_reg(inst.rd, tmp); }, RISCV_LD_LW | RISCV_LD_LWU => { let tmp = Self::read_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64) as usize) as i64; - machine.int_reg.set_reg(inst.rd as usize, tmp); + machine.int_reg.set_reg(inst.rd, tmp); }, RISCV_LD_LD => { let tmp = Self::read_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64) as usize) as i64; - machine.int_reg.set_reg(inst.rd as usize, tmp); + machine.int_reg.set_reg(inst.rd, tmp); }, _ => panic!("In LD switch case, this should never happen... Instr was {}", inst.value) } @@ -364,16 +364,16 @@ impl Machine { /// Executes RISC-V Integer Register-Immediate Instructions on the machine fn opi_instruction(machine: &mut Machine, inst: Instruction) -> Result<(), MachineError> { match inst.funct3 { - RISCV_OPI_ADDI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64), - RISCV_OPI_SLTI => machine.int_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1) < inst.imm12_I_signed as i64) as i64), - RISCV_OPI_XORI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) ^ inst.imm12_I_signed as i64), - RISCV_OPI_ORI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) | inst.imm12_I_signed as i64), - RISCV_OPI_ANDI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) & inst.imm12_I_signed as i64), - RISCV_OPI_SLLI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) << inst.shamt), + RISCV_OPI_ADDI => machine.int_reg.set_reg(inst.rd, machine.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64), + RISCV_OPI_SLTI => machine.int_reg.set_reg(inst.rd, (machine.int_reg.get_reg(inst.rs1) < inst.imm12_I_signed as i64) as i64), + RISCV_OPI_XORI => machine.int_reg.set_reg(inst.rd, machine.int_reg.get_reg(inst.rs1) ^ inst.imm12_I_signed as i64), + RISCV_OPI_ORI => machine.int_reg.set_reg(inst.rd, machine.int_reg.get_reg(inst.rs1) | inst.imm12_I_signed as i64), + RISCV_OPI_ANDI => machine.int_reg.set_reg(inst.rd, machine.int_reg.get_reg(inst.rs1) & inst.imm12_I_signed as i64), + RISCV_OPI_SLLI => machine.int_reg.set_reg(inst.rd, machine.int_reg.get_reg(inst.rs1) << inst.shamt), RISCV_OPI_SRI => if inst.funct7_smaller == RISCV_OPI_SRI_SRLI { - machine.int_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1) >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64); + machine.int_reg.set_reg(inst.rd, (machine.int_reg.get_reg(inst.rs1) >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64); } else { // SRAI - machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) >> inst.shamt); + machine.int_reg.set_reg(inst.rd, machine.int_reg.get_reg(inst.rs1) >> inst.shamt); }, _ => panic!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value) } @@ -389,52 +389,52 @@ impl Machine { match inst.funct3 { RISCV_OP_M_MUL => { long_result = (machine.int_reg.get_reg(inst.rs1) * machine.int_reg.get_reg(inst.rs2)) as i128; - machine.int_reg.set_reg(inst.rd as usize, (long_result & 0xffffffffffffffff) as i64) + machine.int_reg.set_reg(inst.rd, (long_result & 0xffffffffffffffff) as i64) }, RISCV_OP_M_MULH => { long_result = (machine.int_reg.get_reg(inst.rs1) * machine.int_reg.get_reg(inst.rs2)) as i128; - machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64) + machine.int_reg.set_reg(inst.rd, ((long_result >> 64) & 0xffffffffffffffff) as i64) }, RISCV_OP_M_MULHSU => { unsigned_reg2 = machine.int_reg.get_reg(inst.rs2) as u64; long_result = (machine.int_reg.get_reg(inst.rs1) as u64 * unsigned_reg2) as i128; - machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64) + machine.int_reg.set_reg(inst.rd, ((long_result >> 64) & 0xffffffffffffffff) as i64) }, RISCV_OP_M_MULHU => { unsigned_reg1 = machine.int_reg.get_reg(inst.rs1) as u64; unsigned_reg2 = machine.int_reg.get_reg(inst.rs2) as u64; long_result = (unsigned_reg1 * unsigned_reg2) as i128; - machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64); + machine.int_reg.set_reg(inst.rd, ((long_result >> 64) & 0xffffffffffffffff) as i64); }, - RISCV_OP_M_DIV => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) / machine.int_reg.get_reg(inst.rs2)), + RISCV_OP_M_DIV => machine.int_reg.set_reg(inst.rd, machine.int_reg.get_reg(inst.rs1) / machine.int_reg.get_reg(inst.rs2)), _ => panic!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n") } } else { match inst.funct3 { RISCV_OP_ADD => if inst.funct7 == RISCV_OP_ADD_ADD { - machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) + machine.int_reg.get_reg(inst.rs2)) + machine.int_reg.set_reg(inst.rd, machine.int_reg.get_reg(inst.rs1) + machine.int_reg.get_reg(inst.rs2)) } else { - machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) - machine.int_reg.get_reg(inst.rs2)) + machine.int_reg.set_reg(inst.rd, machine.int_reg.get_reg(inst.rs1) - machine.int_reg.get_reg(inst.rs2)) }, - RISCV_OP_SLL => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) << (machine.int_reg.get_reg(inst.rs2) & 0x3f)), + RISCV_OP_SLL => machine.int_reg.set_reg(inst.rd, machine.int_reg.get_reg(inst.rs1) << (machine.int_reg.get_reg(inst.rs2) & 0x3f)), RISCV_OP_SLT => if machine.int_reg.get_reg(inst.rs1) < machine.int_reg.get_reg(inst.rs2) { - machine.int_reg.set_reg(inst.rd as usize, 1) + machine.int_reg.set_reg(inst.rd, 1) } else { - machine.int_reg.set_reg(inst.rd as usize, 0) + machine.int_reg.set_reg(inst.rd, 0) }, RISCV_OP_SLTU => { unsigned_reg1 = machine.int_reg.get_reg(inst.rs1) as u64; unsigned_reg2 = machine.int_reg.get_reg(inst.rs2) as u64; if unsigned_reg1 < unsigned_reg2 { - machine.int_reg.set_reg(inst.rd as usize, 1) + machine.int_reg.set_reg(inst.rd, 1) } else { - machine.int_reg.set_reg(inst.rd as usize, 0) + machine.int_reg.set_reg(inst.rd, 0) } }, - RISCV_OP_XOR => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) ^ machine.int_reg.get_reg(inst.rs2)), - RISCV_OP_SR => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) >> machine.int_reg.get_reg(inst.rs2)), // RISCV_OP_SR_SRL inaccessible - RISCV_OP_OR => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) | machine.int_reg.get_reg(inst.rs2)), - RISCV_OP_AND => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) & machine.int_reg.get_reg(inst.rs2)), + RISCV_OP_XOR => machine.int_reg.set_reg(inst.rd, machine.int_reg.get_reg(inst.rs1) ^ machine.int_reg.get_reg(inst.rs2)), + RISCV_OP_SR => machine.int_reg.set_reg(inst.rd, machine.int_reg.get_reg(inst.rs1) >> machine.int_reg.get_reg(inst.rs2)), // RISCV_OP_SR_SRL inaccessible + RISCV_OP_OR => machine.int_reg.set_reg(inst.rd, machine.int_reg.get_reg(inst.rs1) | machine.int_reg.get_reg(inst.rs2)), + RISCV_OP_AND => machine.int_reg.set_reg(inst.rd, machine.int_reg.get_reg(inst.rs1) & machine.int_reg.get_reg(inst.rs2)), _ => panic!("RISCV_OP undefined case\n") } } @@ -447,11 +447,11 @@ impl Machine { match inst.funct3 { RISCV_OPIW_ADDIW => { let result = local_data + inst.imm12_I_signed as i64; - machine.int_reg.set_reg(inst.rd as usize, result) + machine.int_reg.set_reg(inst.rd, result) }, RISCV_OPIW_SLLIW => { let result = local_data << inst.shamt; - machine.int_reg.set_reg(inst.rd as usize, result) + machine.int_reg.set_reg(inst.rd, result) }, RISCV_OPIW_SRW => { let result = if inst.funct7 == RISCV_OPIW_SRW_SRLIW { @@ -459,7 +459,7 @@ impl Machine { } else { // SRAIW local_data >> inst.shamt }; - machine.int_reg.set_reg(inst.rd as usize, result) + machine.int_reg.set_reg(inst.rd, result) }, _ => panic!("In OPI switch case, this should never happen... Instr was {}\n", inst.value), } @@ -476,11 +476,11 @@ impl Machine { // Match case for multiplication operations (in standard extension RV32M) match inst.funct3 { - RISCV_OPW_M_MULW => machine.int_reg.set_reg(inst.rd as usize, local_data_a * local_data_b), - RISCV_OPW_M_DIVW => machine.int_reg.set_reg(inst.rd as usize, local_data_a / local_data_b), - RISCV_OPW_M_DIVUW => machine.int_reg.set_reg(inst.rd as usize, local_data_a_unsigned / local_data_b_unsigned), - RISCV_OPW_M_REMW => machine.int_reg.set_reg(inst.rd as usize, local_data_a % local_data_b), - RISCV_OPW_M_REMUW => machine.int_reg.set_reg(inst.rd as usize, local_data_a_unsigned % local_data_b_unsigned), + RISCV_OPW_M_MULW => machine.int_reg.set_reg(inst.rd, local_data_a * local_data_b), + RISCV_OPW_M_DIVW => machine.int_reg.set_reg(inst.rd, local_data_a / local_data_b), + RISCV_OPW_M_DIVUW => machine.int_reg.set_reg(inst.rd, local_data_a_unsigned / local_data_b_unsigned), + RISCV_OPW_M_REMW => machine.int_reg.set_reg(inst.rd, local_data_a % local_data_b), + RISCV_OPW_M_REMUW => machine.int_reg.set_reg(inst.rd, local_data_a_unsigned % local_data_b_unsigned), _ => panic!("this instruction ({}) doesn't exists", inst.value) } } else { // others rv64 OPW operations @@ -489,15 +489,15 @@ impl Machine { // Match case for base OP operation match inst.funct3 { RISCV_OPW_ADDSUBW => if inst.funct7 == RISCV_OPW_ADDSUBW_ADDW { - machine.int_reg.set_reg(inst.rd as usize, local_dataa + local_datab); + machine.int_reg.set_reg(inst.rd, local_dataa + local_datab); } else { // SUBW - machine.int_reg.set_reg(inst.rd as usize, local_dataa - local_datab); + machine.int_reg.set_reg(inst.rd, local_dataa - local_datab); }, - RISCV_OPW_SLLW => machine.int_reg.set_reg(inst.rd as usize, local_dataa << (local_datab & 0x1f)), + RISCV_OPW_SLLW => machine.int_reg.set_reg(inst.rd, local_dataa << (local_datab & 0x1f)), RISCV_OPW_SRW => if inst.funct7 == RISCV_OPW_SRW_SRLW { - machine.int_reg.set_reg(inst.rd as usize, local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize] as i64) + machine.int_reg.set_reg(inst.rd, local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize] as i64) } else { // SRAW - machine.int_reg.set_reg(inst.rd as usize, local_dataa >> (local_datab & 0x1f)) + machine.int_reg.set_reg(inst.rd, local_dataa >> (local_datab & 0x1f)) }, _ => panic!("this instruction ({}) doesn't exists", inst.value) } @@ -508,29 +508,29 @@ impl Machine { /// Executes simple RISC-V floating point instructions on the machine fn fp_instruction(machine: &mut Machine, inst: Instruction) -> Result<(), MachineError> { match inst.funct7 { - RISCV_FP_ADD => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1) + machine.fp_reg.get_reg(inst.rs2)), - RISCV_FP_SUB => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1) - machine.fp_reg.get_reg(inst.rs2)), - RISCV_FP_MUL => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1) * machine.fp_reg.get_reg(inst.rs2)), - RISCV_FP_DIV => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1) / machine.fp_reg.get_reg(inst.rs2)), - RISCV_FP_SQRT => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1).sqrt()), + RISCV_FP_ADD => machine.fp_reg.set_reg(inst.rd, machine.fp_reg.get_reg(inst.rs1) + machine.fp_reg.get_reg(inst.rs2)), + RISCV_FP_SUB => machine.fp_reg.set_reg(inst.rd, machine.fp_reg.get_reg(inst.rs1) - machine.fp_reg.get_reg(inst.rs2)), + RISCV_FP_MUL => machine.fp_reg.set_reg(inst.rd, machine.fp_reg.get_reg(inst.rs1) * machine.fp_reg.get_reg(inst.rs2)), + RISCV_FP_DIV => machine.fp_reg.set_reg(inst.rd, machine.fp_reg.get_reg(inst.rs1) / machine.fp_reg.get_reg(inst.rs2)), + RISCV_FP_SQRT => machine.fp_reg.set_reg(inst.rd, machine.fp_reg.get_reg(inst.rs1).sqrt()), RISCV_FP_FSGN => { let local_float = machine.fp_reg.get_reg(inst.rs1); match inst.funct3 { RISCV_FP_FSGN_J => if machine.fp_reg.get_reg(inst.rs2) < 0f32 { - machine.fp_reg.set_reg(inst.rd as usize, -local_float) + machine.fp_reg.set_reg(inst.rd, -local_float) } else { - machine.fp_reg.set_reg(inst.rd as usize, local_float) + machine.fp_reg.set_reg(inst.rd, local_float) }, RISCV_FP_FSGN_JN => if machine.fp_reg.get_reg(inst.rs2) < 0f32 { - machine.fp_reg.set_reg(inst.rd as usize, local_float) + machine.fp_reg.set_reg(inst.rd, local_float) } else { - machine.fp_reg.set_reg(inst.rd as usize, -local_float) + machine.fp_reg.set_reg(inst.rd, -local_float) }, RISCV_FP_FSGN_JX => if (machine.fp_reg.get_reg(inst.rs2) < 0.0 && machine.fp_reg.get_reg(inst.rs1) >= 0.0) || (machine.fp_reg.get_reg(inst.rs2) >= 0.0 && machine.fp_reg.get_reg(inst.rs1) < 0.0) { - machine.fp_reg.set_reg(inst.rd as usize, -local_float) + machine.fp_reg.set_reg(inst.rd, -local_float) } else { - machine.fp_reg.set_reg(inst.rd as usize, local_float) + machine.fp_reg.set_reg(inst.rd, local_float) }, _ => panic!("this instruction ({}) doesn't exists", inst.value) } @@ -539,38 +539,38 @@ impl Machine { let r1 = machine.fp_reg.get_reg(inst.rs1); let r2 = machine.fp_reg.get_reg(inst.rs2); match inst.funct3 { - RISCV_FP_MINMAX_MIN => machine.fp_reg.set_reg(inst.rd as usize, if r1 < r2 {r1} else {r2}), - RISCV_FP_MINMAX_MAX => machine.fp_reg.set_reg(inst.rd as usize, if r1 > r2 {r1} else {r2}), + RISCV_FP_MINMAX_MIN => machine.fp_reg.set_reg(inst.rd, if r1 < r2 {r1} else {r2}), + RISCV_FP_MINMAX_MAX => machine.fp_reg.set_reg(inst.rd, if r1 > r2 {r1} else {r2}), _ => panic!("this instruction ({}) doesn't exists", inst.value) } }, RISCV_FP_FCVTW => { if inst.rs2 == RISCV_FP_FCVTW_W { - machine.int_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1) as i64) + machine.int_reg.set_reg(inst.rd, machine.fp_reg.get_reg(inst.rs1) as i64) } else { - machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1) as u64) as i64) + machine.int_reg.set_reg(inst.rd, (machine.fp_reg.get_reg(inst.rs1) as u64) as i64) } }, RISCV_FP_FCVTS => { if inst.rs2 == RISCV_FP_FCVTS_W { - machine.fp_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) as f32); + machine.fp_reg.set_reg(inst.rd, machine.int_reg.get_reg(inst.rs1) as f32); } else { - machine.fp_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1) as u32) as f32); + machine.fp_reg.set_reg(inst.rd, (machine.int_reg.get_reg(inst.rs1) as u32) as f32); } }, - RISCV_FP_FMVW => machine.fp_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) as f32), + RISCV_FP_FMVW => machine.fp_reg.set_reg(inst.rd, machine.int_reg.get_reg(inst.rs1) as f32), RISCV_FP_FMVXFCLASS => { if inst.funct3 == RISCV_FP_FMVXFCLASS_FMVX { - machine.int_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1) as i64); + machine.int_reg.set_reg(inst.rd, machine.fp_reg.get_reg(inst.rs1) as i64); } else { panic!("Fclass instruction is not handled in riscv simulator"); } }, RISCV_FP_FCMP => { match inst.funct3 { - RISCV_FP_FCMP_FEQ => machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1) == machine.fp_reg.get_reg(inst.rs2)) as i64), - RISCV_FP_FCMP_FLT => machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1) < machine.fp_reg.get_reg(inst.rs2)) as i64), - RISCV_FP_FCMP_FLE => machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1) <= machine.fp_reg.get_reg(inst.rs2)) as i64), + RISCV_FP_FCMP_FEQ => machine.int_reg.set_reg(inst.rd, (machine.fp_reg.get_reg(inst.rs1) == machine.fp_reg.get_reg(inst.rs2)) as i64), + RISCV_FP_FCMP_FLT => machine.int_reg.set_reg(inst.rd, (machine.fp_reg.get_reg(inst.rs1) < machine.fp_reg.get_reg(inst.rs2)) as i64), + RISCV_FP_FCMP_FLE => machine.int_reg.set_reg(inst.rd, (machine.fp_reg.get_reg(inst.rs1) <= machine.fp_reg.get_reg(inst.rs2)) as i64), _ => panic!("this instruction ({}) doesn't exists", inst.value) } }, @@ -604,12 +604,12 @@ impl Machine { /// Write into int register pub fn write_int_register(&mut self, index: usize, value: i64) { - self.int_reg.set_reg(index, value); + self.int_reg.set_reg(index as u8, value); } /// Write info float register pub fn write_fp_register(&mut self, index: usize, value: f32) { - self.fp_reg.set_reg(index, value); + self.fp_reg.set_reg(index as u8, value); } } diff --git a/src/simulator/register.rs b/src/simulator/register.rs index 2f78d30..a0ef372 100644 --- a/src/simulator/register.rs +++ b/src/simulator/register.rs @@ -26,8 +26,8 @@ impl Register { /// /// Checking against trying to set a new value to the 0th register /// as its value is NOT supposed to change - pub fn set_reg(&mut self, position: usize, value: U) { - if position != 0 { self.register[position] = value; } + pub fn set_reg(&mut self, position: u8, value: U) { + if position != 0 { self.register[position as usize] = value; } }