Align with tabulations
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parent
dcd2012c64
commit
802f80e96a
118
src/print.rs
118
src/print.rs
@ -181,33 +181,33 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
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name = names_op[ins.funct3 as usize];
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}
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}
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format!("{} {}, {}, {}", name.to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2])
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format!("{}\t{}, {}, {}", name.to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2])
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},
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RISCV_OPI => {
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// SHAMT OR IMM
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if ins.funct3 == RISCV_OPI_SRI {
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if ins.funct7 == RISCV_OPI_SRI_SRLI {
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format!("slrii {}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string())
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format!("slrii\t{}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string())
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} else {
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format!("srai {}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string())
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format!("srai\t{}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string())
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}
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} else if ins.funct3 == RISCV_OPI_SLLI {
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format!("{} {}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.shamt.to_string())
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format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.shamt.to_string())
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} else {
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format!("{} {}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string())
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format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string())
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}
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},
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RISCV_LUI => {
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format!("lui {}, 0x{:X}", reg_x[rd], ins.imm31_12)
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format!("lui\t{}, 0x{:X}", reg_x[rd], ins.imm31_12)
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},
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RISCV_AUIPC => {
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format!("auipc {}, {:X}", reg_x[rd], ins.imm31_12)
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format!("auipc\t{}, {:X}", reg_x[rd], ins.imm31_12)
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},
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RISCV_JAL => {
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if ins.rd == 0 {
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format!("j {}", ins.imm31_12.to_string())
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format!("j\t{}", ins.imm31_12.to_string())
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} else {
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format!("jal {}, {:X}", reg_x[rd], (pc - 4 + ins.imm21_1_signed))
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format!("jal\t{}, {:X}", reg_x[rd], (pc - 4 + ins.imm21_1_signed))
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}
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},
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RISCV_JALR => {
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@ -215,52 +215,52 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
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if ins.rs1 == 1 {
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"ret".to_string()
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} else {
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format!("jr {:X}", ins.imm31_12)
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format!("jr\t{:X}", ins.imm31_12)
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}
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} else {
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format!("jalr {}, ({})", ins.imm12_I_signed.to_string(), reg_x[rs1])
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format!("jalr\t{}, ({})", ins.imm12_I_signed.to_string(), reg_x[rs1])
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}
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},
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RISCV_BR => {
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format!("{} {}, {}, {}", names_br[ins.funct3 as usize].to_string(), reg_x[rs1], reg_x[rs2], ins.imm13_signed.to_string())
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format!("{}\t{}, {}, {}", names_br[ins.funct3 as usize].to_string(), reg_x[rs1], reg_x[rs2], ins.imm13_signed.to_string())
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},
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RISCV_LD => {
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format!("{} {}, {}({})", names_ld[ins.funct3 as usize].to_string(), reg_x[rd], ins.imm12_I_signed.to_string(), reg_x[rs1])
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format!("{}\t{}, {}({})", names_ld[ins.funct3 as usize].to_string(), reg_x[rd], ins.imm12_I_signed.to_string(), reg_x[rs1])
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},
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RISCV_ST => {
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format!("{} {}, {}({})", names_st[ins.funct3 as usize].to_string(), reg_x[rs2], ins.imm12_S_signed.to_string(), reg_x[rs1])
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format!("{}\t{}, {}({})", names_st[ins.funct3 as usize].to_string(), reg_x[rs2], ins.imm12_S_signed.to_string(), reg_x[rs1])
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},
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RISCV_OPIW => {
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if ins.funct3 == RISCV_OPIW_SRW {
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if ins.funct7 == RISCV_OPIW_SRW_SRLIW {
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format!("srlwi {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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format!("srlwi\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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} else {
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format!("srawi {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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format!("srawi\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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}
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} else if ins.funct3 == RISCV_OPIW_SLLIW {
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format!("{} {}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2])
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format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2])
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} else {
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format!("{} {}, {}, {}", names_opiw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string())
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format!("{}\t{}, {}, {}", names_opiw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string())
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}
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},
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RISCV_OPW => {
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if ins.funct7 == 1 {
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format!("{}w {}, {}, {}", names_mul[ins.funct3 as usize].to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2])
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format!("{}w\t{}, {}, {}", names_mul[ins.funct3 as usize].to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2])
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} else {
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if ins.funct3 == RISCV_OP_ADD {
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if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW {
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format!("addw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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format!("addw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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} else {
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format!("subw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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format!("subw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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}
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} else if ins.funct3 == RISCV_OPW_SRW {
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if ins.funct7 == RISCV_OPW_SRW_SRLW {
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format!("srlw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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format!("srlw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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} else {
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format!("sraw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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format!("sraw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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}
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} else {
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format!("{} {}, {}, {}", names_opw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2])
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format!("{}\t{}, {}, {}", names_opw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2])
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}
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}
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},
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@ -286,11 +286,11 @@ mod test {
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let slr = decode::decode(0b0000000_10000_10001_101_11100_0110011);
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let sra = decode::decode(0b0100000_10000_10001_101_11100_0110011);
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assert_eq!("sub t3, a7, a6", print::print(sub, 0));
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assert_eq!("xor t3, a7, a6", print::print(xor, 0));
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assert_eq!("srl t3, a7, a6", print::print(slr, 0));
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assert_eq!("sra t3, a7, a6", print::print(sra, 0));
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assert_eq!("add t3, a7, a6", print::print(add, 0));
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assert_eq!("sub\tt3, a7, a6", print::print(sub, 0));
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assert_eq!("xor\tt3, a7, a6", print::print(xor, 0));
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assert_eq!("srl\tt3, a7, a6", print::print(slr, 0));
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assert_eq!("sra\tt3, a7, a6", print::print(sra, 0));
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assert_eq!("add\tt3, a7, a6", print::print(add, 0));
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}
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@ -303,21 +303,21 @@ mod test {
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let xori = decode::decode(0b_0000000000010001_100_11100_0010011);
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let ori = decode::decode(0b00000000000_10001_110_11100_0010011);
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let andi = decode::decode(0b000000000000_10001_111_11100_0010011);
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assert_eq!("andi t3, a7, 0", print::print(andi, 0));
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assert_eq!("addi t3, a7, 0", print::print(addi, 0));
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assert_eq!("slli t3, a7, 0", print::print(slli, 0));
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assert_eq!("slti t3, a7, 0", print::print(slti, 0));
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assert_eq!("sltiu t3, a7, 0", print::print(sltiu, 0));
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assert_eq!("xori t3, a7, 0", print::print(xori, 0));
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assert_eq!("ori t3, a7, 0", print::print(ori, 0));
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assert_eq!("andi\tt3, a7, 0", print::print(andi, 0));
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assert_eq!("addi\tt3, a7, 0", print::print(addi, 0));
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assert_eq!("slli\tt3, a7, 0", print::print(slli, 0));
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assert_eq!("slti\tt3, a7, 0", print::print(slti, 0));
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assert_eq!("sltiu\tt3, a7, 0", print::print(sltiu, 0));
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assert_eq!("xori\tt3, a7, 0", print::print(xori, 0));
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assert_eq!("ori\tt3, a7, 0", print::print(ori, 0));
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}
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#[test]
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fn test_lui() {
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let lui = decode::decode(0b01110001000011111000_11100_0110111);
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let lui_negatif = decode::decode(0b11110001000011111000_11100_0110111);
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assert_eq!("lui t3, 0x710F8000", print::print(lui, 0));
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assert_eq!("lui t3, 0xF10F8000", print::print(lui_negatif, 0));
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assert_eq!("lui\tt3, 0x710F8000", print::print(lui, 0));
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assert_eq!("lui\tt3, 0xF10F8000", print::print(lui_negatif, 0));
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}
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#[test]
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@ -330,14 +330,14 @@ mod test {
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let lhu = decode::decode(0b010111110000_10001_101_11100_0000011);
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let ld = decode::decode(0b010111110000_10001_011_11100_0000011);
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let lwu = decode::decode(0b010111110000_10001_110_11100_0000011);
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// TODO: imm négatif produit une erreur
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assert_eq!("lb t3, 1520(a7)", print::print(lb, 0));
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assert_eq!("lh t3, 1520(a7)", print::print(lh, 0));
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assert_eq!("lw t3, 1520(a7)", print::print(lw, 0));
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assert_eq!("lbu t3, 1520(a7)", print::print(lbu, 0));
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assert_eq!("lhu t3, 1520(a7)", print::print(lhu, 0));
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assert_eq!("ld t3, 1520(a7)", print::print(ld, 0));
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assert_eq!("lwu t3, 1520(a7)", print::print(lwu, 0));
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assert_eq!("lb\tt3, 1520(a7)", print::print(lb, 0));
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assert_eq!("lh\tt3, 1520(a7)", print::print(lh, 0));
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assert_eq!("lw\tt3, 1520(a7)", print::print(lw, 0));
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assert_eq!("lbu\tt3, 1520(a7)", print::print(lbu, 0));
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assert_eq!("lhu\tt3, 1520(a7)", print::print(lhu, 0));
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assert_eq!("ld\tt3, 1520(a7)", print::print(ld, 0));
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assert_eq!("lwu\tt3, 1520(a7)", print::print(lwu, 0));
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}
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#[test]
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@ -347,10 +347,10 @@ mod test {
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let srlw: decode::Instruction = decode::decode(0b0000000_10000_10001_101_11100_0111011);
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let sraw: decode::Instruction = decode::decode(0b0100000_10000_10001_101_11100_0111011);
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assert_eq!("addw t3, a7, a6", print::print(addw, 0));
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assert_eq!("sllw t3, a7, a6", print::print(sllw, 0));
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assert_eq!("srlw t3, a7, a6", print::print(srlw, 0));
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assert_eq!("sraw t3, a7, a6", print::print(sraw, 0));
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assert_eq!("addw\tt3, a7, a6", print::print(addw, 0));
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assert_eq!("sllw\tt3, a7, a6", print::print(sllw, 0));
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assert_eq!("srlw\tt3, a7, a6", print::print(srlw, 0));
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assert_eq!("sraw\tt3, a7, a6", print::print(sraw, 0));
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}
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#[test]
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@ -358,9 +358,9 @@ mod test {
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let addiw: decode::Instruction =decode::decode(0b000000000000_10001_000_11100_0011011);
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let slliw: decode::Instruction = decode::decode(0b0000000_10000_10001_001_11100_0011011);
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let srai: decode::Instruction = decode::decode(0b010000010001_10001_101_11100_0010011);
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assert_eq!("addiw t3, a7, 0", print::print(addiw, 0));
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assert_eq!("slli t3, a7, a6", print::print(slliw, 0));
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assert_eq!("srai t3, a7, 17", print::print(srai, 0));
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assert_eq!("addiw\tt3, a7, 0", print::print(addiw, 0));
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assert_eq!("slli\tt3, a7, a6", print::print(slliw, 0));
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assert_eq!("srai\tt3, a7, 17", print::print(srai, 0));
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}
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@ -372,12 +372,12 @@ mod test {
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let bge: decode::Instruction = decode::decode(0b0000000_10000_10001_101_00000_1100011);
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let bltu: decode::Instruction = decode::decode(0b0000000_10000_10001_110_00000_1100011);
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let bgeu: decode::Instruction = decode::decode(0b0000000_10000_10001_111_00000_1100011);
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assert_eq!("blt a7, a6, 0", print::print(blt, 0));
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assert_eq!("bge a7, a6, 0", print::print(bge, 0));
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assert_eq!("bltu a7, a6, 0", print::print(bltu, 0));
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assert_eq!("bgeu a7, a6, 0", print::print(bgeu, 0));
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assert_eq!("bne a7, a6, 0", print::print(bne, 0));
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assert_eq!("beq a7, a6, 0", print::print(beq, 0));
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assert_eq!("blt\ta7, a6, 0", print::print(blt, 0));
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assert_eq!("bge\ta7, a6, 0", print::print(bge, 0));
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assert_eq!("bltu\ta7, a6, 0", print::print(bltu, 0));
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assert_eq!("bgeu\ta7, a6, 0", print::print(bgeu, 0));
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assert_eq!("bne\ta7, a6, 0", print::print(bne, 0));
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assert_eq!("beq\ta7, a6, 0", print::print(beq, 0));
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}
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}
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