From f9046f411aceae85c6d6a2693bc8b2bccc0d411c Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Tue, 7 Feb 2023 21:58:02 +0100 Subject: [PATCH 1/3] Fixed print for BR --- src/simulator/print.rs | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/simulator/print.rs b/src/simulator/print.rs index 4bad5ad..a76fbd6 100644 --- a/src/simulator/print.rs +++ b/src/simulator/print.rs @@ -80,7 +80,7 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 format!("jalr\t{},{}({})", REG_X[rd], ins.imm12_I_signed, REG_X[rs1]) }, RISCV_BR => { - format!("{}\t{}, {}, {}", NAMES_BR[ins.funct3 as usize], REG_X[rs1], REG_X[rs2], ins.imm13_signed) + format!("{}\t{},{},{:x}", NAMES_BR[ins.funct3 as usize], REG_X[rs1], REG_X[rs2], pc + (ins.imm13_signed as i32)) }, RISCV_LD => { format!("{}\t{},{}({})", NAMES_LD[ins.funct3 as usize], REG_X[rd], ins.imm12_I_signed, REG_X[rs1]) @@ -230,12 +230,12 @@ mod test { let bge: decode::Instruction = decode::decode(0b0000000_10000_10001_101_00000_1100011); let bltu: decode::Instruction = decode::decode(0b0000000_10000_10001_110_00000_1100011); let bgeu: decode::Instruction = decode::decode(0b0000000_10000_10001_111_00000_1100011); - assert_eq!("blt\ta7, a6, 0", print::print(blt, 0)); - assert_eq!("bge\ta7, a6, 0", print::print(bge, 0)); - assert_eq!("bltu\ta7, a6, 0", print::print(bltu, 0)); - assert_eq!("bgeu\ta7, a6, 0", print::print(bgeu, 0)); - assert_eq!("bne\ta7, a6, 0", print::print(bne, 0)); - assert_eq!("beq\ta7, a6, 0", print::print(beq, 0)); + assert_eq!("blt\ta7,a6,0", print::print(blt, 0)); + assert_eq!("bge\ta7,a6,0", print::print(bge, 0)); + assert_eq!("bltu\ta7,a6,0", print::print(bltu, 0)); + assert_eq!("bgeu\ta7,a6,0", print::print(bgeu, 0)); + assert_eq!("bne\ta7,a6,0", print::print(bne, 0)); + assert_eq!("beq\ta7,a6,0", print::print(beq, 0)); } #[test] @@ -283,7 +283,7 @@ mod test { #[test] fn test_fibo() { assert_eq!("jal zero,10504", print::print(decode::decode(0x0500006f), 0x104b4)); - //assert_eq!("blt a4,a5,104b8", print::print(decode::decode(0xfaf740e3), 0x10518)); + assert_eq!("blt a4,a5,104b8", print::print(decode::decode(0xfaf740e3), 0x10518)); } } \ No newline at end of file From 89aaa4e821da2a88f86eb4e5706d913c401e94b3 Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Tue, 7 Feb 2023 22:00:53 +0100 Subject: [PATCH 2/3] Changed hexa format to lowercase --- src/simulator/print.rs | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/simulator/print.rs b/src/simulator/print.rs index a76fbd6..e6d5a54 100644 --- a/src/simulator/print.rs +++ b/src/simulator/print.rs @@ -68,13 +68,13 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 } }, RISCV_LUI => { - format!("lui\t{}, 0x{:X}", REG_X[rd], ins.imm31_12) + format!("lui\t{}, 0x{:x}", REG_X[rd], ins.imm31_12) }, RISCV_AUIPC => { - format!("auipc\t{}, {:X}", REG_X[rd], ins.imm31_12) + format!("auipc\t{}, {:x}", REG_X[rd], ins.imm31_12) }, RISCV_JAL => { - format!("jal\t{},{:X}", REG_X[rd], (pc + ins.imm21_1_signed)) + format!("jal\t{},{:x}", REG_X[rd], (pc + ins.imm21_1_signed)) }, RISCV_JALR => { format!("jalr\t{},{}({})", REG_X[rd], ins.imm12_I_signed, REG_X[rs1]) @@ -174,8 +174,8 @@ mod test { fn test_lui() { let lui = decode::decode(0b01110001000011111000_11100_0110111); let lui_negatif = decode::decode(0b11110001000011111000_11100_0110111); - assert_eq!("lui\tt3, 0x710F8000", print::print(lui, 0)); - assert_eq!("lui\tt3, 0xF10F8000", print::print(lui_negatif, 0)); + assert_eq!("lui\tt3, 0x710f8000", print::print(lui, 0)); + assert_eq!("lui\tt3, 0xf10f8000", print::print(lui_negatif, 0)); } #[test] From 4438218d339a2aba45d2573914e4ab2ede3b4295 Mon Sep 17 00:00:00 2001 From: Samy Solhi Date: Tue, 7 Feb 2023 22:05:35 +0100 Subject: [PATCH 3/3] Removed wrong spaces --- src/simulator/print.rs | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/src/simulator/print.rs b/src/simulator/print.rs index e6d5a54..6e18925 100644 --- a/src/simulator/print.rs +++ b/src/simulator/print.rs @@ -51,15 +51,15 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 } else { name = NAMES_OP[ins.funct3 as usize]; } - format!("{}\t{}, {}, {}", name, REG_X[rd], REG_X[rs1], REG_X[rs2]) + format!("{}\t{},{},{}", name, REG_X[rd], REG_X[rs1], REG_X[rs2]) }, RISCV_OPI => { // SHAMT OR IMM if ins.funct3 == RISCV_OPI_SRI { if ins.funct7 == RISCV_OPI_SRI_SRLI { - format!("srli\t{}, {}, {}", REG_X[rd], REG_X[rs1], ins.shamt) + format!("srli\t{},{},{}", REG_X[rd], REG_X[rs1], ins.shamt) } else { - format!("srai\t{}, {}, {}", REG_X[rd], REG_X[rs1], ins.shamt) + format!("srai\t{},{},{}", REG_X[rd], REG_X[rs1], ins.shamt) } } else if ins.funct3 == RISCV_OPI_SLLI { format!("{}\t{},{},{}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.shamt) @@ -68,10 +68,10 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 } }, RISCV_LUI => { - format!("lui\t{}, 0x{:x}", REG_X[rd], ins.imm31_12) + format!("lui\t{},{:x}", REG_X[rd], ins.imm31_12) }, RISCV_AUIPC => { - format!("auipc\t{}, {:x}", REG_X[rd], ins.imm31_12) + format!("auipc\t{},{:x}", REG_X[rd], ins.imm31_12) }, RISCV_JAL => { format!("jal\t{},{:x}", REG_X[rd], (pc + ins.imm21_1_signed)) @@ -91,19 +91,19 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 RISCV_OPIW => { if ins.funct3 == RISCV_OPIW_SRW { if ins.funct7 == RISCV_OPIW_SRW_SRLIW { - format!("srliw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) + format!("srliw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2]) } else { - format!("sraiw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) + format!("sraiw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2]) } } else if ins.funct3 == RISCV_OPIW_SLLIW { - format!("{}\t{}, {}, {}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) + format!("{}\t{},{},{}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) } else { - format!("{}\t{}, {}, {}", NAMES_OPIW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed) + format!("{}\t{},{},{}", NAMES_OPIW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed) } }, RISCV_OPW => { if ins.funct7 == 1 { - format!("{}w\t{}, {}, {}", NAMES_MUL[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) + format!("{}w\t{},{},{}", NAMES_MUL[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) } else if ins.funct3 == RISCV_OP_ADD { if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW { format!("addw\t{},{},{}", REG_X[rd], REG_X[rs1], REG_X[rs2]) @@ -144,11 +144,11 @@ mod test { let slr = decode::decode(0b0000000_10000_10001_101_11100_0110011); let sra = decode::decode(0b0100000_10000_10001_101_11100_0110011); - assert_eq!("sub\tt3, a7, a6", print::print(sub, 0)); - assert_eq!("xor\tt3, a7, a6", print::print(xor, 0)); - assert_eq!("srl\tt3, a7, a6", print::print(slr, 0)); - assert_eq!("sra\tt3, a7, a6", print::print(sra, 0)); - assert_eq!("add\tt3, a7, a6", print::print(add, 0)); + assert_eq!("sub\tt3,a7,a6", print::print(sub, 0)); + assert_eq!("xor\tt3,a7,a6", print::print(xor, 0)); + assert_eq!("srl\tt3,a7,a6", print::print(slr, 0)); + assert_eq!("sra\tt3,a7,a6", print::print(sra, 0)); + assert_eq!("add\tt3,a7,a6", print::print(add, 0)); } @@ -174,8 +174,8 @@ mod test { fn test_lui() { let lui = decode::decode(0b01110001000011111000_11100_0110111); let lui_negatif = decode::decode(0b11110001000011111000_11100_0110111); - assert_eq!("lui\tt3, 0x710f8000", print::print(lui, 0)); - assert_eq!("lui\tt3, 0xf10f8000", print::print(lui_negatif, 0)); + assert_eq!("lui\tt3,710f8000", print::print(lui, 0)); + assert_eq!("lui\tt3,f10f8000", print::print(lui_negatif, 0)); } #[test] @@ -216,9 +216,9 @@ mod test { let addiw: decode::Instruction =decode::decode(0b000000000000_10001_000_11100_0011011); let slliw: decode::Instruction = decode::decode(0b0000000_10000_10001_001_11100_0011011); let srai: decode::Instruction = decode::decode(0b010000010001_10001_101_11100_0010011); - assert_eq!("addiw\tt3, a7, 0", print::print(addiw, 0)); - assert_eq!("slli\tt3, a7, a6", print::print(slliw, 0)); - assert_eq!("srai\tt3, a7, 17", print::print(srai, 0)); + assert_eq!("addiw\tt3,a7,0", print::print(addiw, 0)); + assert_eq!("slli\tt3,a7,a6", print::print(slliw, 0)); + assert_eq!("srai\tt3,a7,17", print::print(srai, 0)); }