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Remove ~60 warnings

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This commit is contained in:
Quentin Legot 2022-11-16 15:48:46 +01:00
parent f9dba1ac11
commit 9a233f3c12
3 changed files with 123 additions and 120 deletions
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24
src/machine.rs
View File

@ -9,7 +9,7 @@ pub struct Machine {
pub pc : u32, pub pc : u32,
pub int_reg : [u32 ; 32], pub int_reg : [u32 ; 32],
pub instructions : [u32 ; 100], pub instructions : [u32 ; 100],
pub mainMemory : [u8 ; MEM_SIZE] pub main_memory : [u8 ; MEM_SIZE]
// futur taille à calculer int memSize = g_cfg->NumPhysPages * g_cfg->PageSize; // futur taille à calculer int memSize = g_cfg->NumPhysPages * g_cfg->PageSize;
//creer une struct cfg(configuration) qui s'initialise avec valeur dans un fichier cfg //creer une struct cfg(configuration) qui s'initialise avec valeur dans un fichier cfg
} }
@ -23,16 +23,16 @@ impl Machine {
pc : 0, pc : 0,
instructions : [0 ; 100], instructions : [0 ; 100],
int_reg : [0 ; 32], int_reg : [0 ; 32],
mainMemory : [0 ; MEM_SIZE] main_memory : [0 ; MEM_SIZE]
} }
} }
pub fn oneInstruction(mut machine : Machine) -> Machine { pub fn one_instruction(mut machine : Machine) -> Machine {
let mut unsignedReg1 : u64 = 0; let mut unsigned_reg1 : u64 = 0;
let mut unsignedReg2 : u64 = 0; let mut unsigned_reg2 : u64 = 0;
if (machine.instructions.len() <= machine.pc as usize) { if machine.instructions.len() <= machine.pc as usize {
println!("ERROR : number max of instructions rushed"); println!("ERROR : number max of instructions rushed");
return machine; return machine;
} }
@ -69,6 +69,7 @@ impl Machine {
RISCV_OPI_SLLI => { RISCV_OPI_SLLI => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt; machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt;
} }
_ => { println!("{} inconnu", inst.funct3); }
} }
}, },
@ -90,16 +91,16 @@ impl Machine {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f); machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f);
}, },
RISCV_OP_SLT => { RISCV_OP_SLT => {
if(machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize]){ if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
machine.int_reg[inst.rd as usize] = 1; machine.int_reg[inst.rd as usize] = 1;
} else { } else {
machine.int_reg[inst.rd as usize] = 0; machine.int_reg[inst.rd as usize] = 0;
} }
}, },
RISCV_OP_SLTU => { RISCV_OP_SLTU => {
unsignedReg1 = machine.int_reg[inst.rs1 as usize] as u64; unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
unsignedReg2 = machine.int_reg[inst.rs2 as usize] as u64; unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
if(unsignedReg1 < unsignedReg2){ if unsigned_reg1 < unsigned_reg2 {
machine.int_reg[inst.rd as usize] = 1; machine.int_reg[inst.rd as usize] = 1;
} else { } else {
machine.int_reg[inst.rd as usize] = 0; machine.int_reg[inst.rd as usize] = 0;
@ -122,7 +123,8 @@ impl Machine {
println!("RISCV_OP undefined case\n"); println!("RISCV_OP undefined case\n");
} }
} }
}, }
_ => { println!("{} opcode non géré", inst.opcode)},
} }

2
src/main.rs
View File

@ -6,5 +6,5 @@ use machine::Machine;
fn main() { fn main() {
let mut m = Machine::_init_machine(); let mut m = Machine::_init_machine();
m.instructions[0] = 0x37; m.instructions[0] = 0x37;
Machine::oneInstruction(m); Machine::one_instruction(m);
} }

215
src/print.rs
View File

@ -2,132 +2,133 @@
#![allow(unused_variables)] #![allow(unused_variables)]
use crate::decode::Instruction; use crate::decode::Instruction;
const RISCV_LUI: u8 = 0x37;
const RISCV_AUIPC: u8 = 0x17; pub const RISCV_LUI: u8 = 0x37;
const RISCV_JAL: u8 = 0x6f; pub const RISCV_AUIPC: u8 = 0x17;
const RISCV_JALR: u8 = 0x67; pub const RISCV_JAL: u8 = 0x6f;
const RISCV_BR: u8 = 0x63; pub const RISCV_JALR: u8 = 0x67;
const RISCV_LD: u8 = 0x3; pub const RISCV_BR: u8 = 0x63;
const RISCV_ST: u8 = 0x23; pub const RISCV_LD: u8 = 0x3;
const RISCV_OPI: u8 = 0x13; pub const RISCV_ST: u8 = 0x23;
const RISCV_OP: u8 = 0x33; pub const RISCV_OPI: u8 = 0x13;
const RISCV_OPIW: u8 = 0x1b; pub const RISCV_OP: u8 = 0x33;
const RISCV_OPW: u8 = 0x3b; pub const RISCV_OPIW: u8 = 0x1b;
pub const RISCV_OPW: u8 = 0x3b;
const RISCV_BR_BEQ: u8 = 0x0; pub const RISCV_BR_BEQ: u8 = 0x0;
const RISCV_BR_BNE: u8 = 0x1; pub const RISCV_BR_BNE: u8 = 0x1;
const RISCV_BR_BLT: u8 = 0x4; pub const RISCV_BR_BLT: u8 = 0x4;
const RISCV_BR_BGE: u8 = 0x5; pub const RISCV_BR_BGE: u8 = 0x5;
const RISCV_BR_BLTU: u8 = 0x6; pub const RISCV_BR_BLTU: u8 = 0x6;
const RISCV_BR_BGEU: u8 = 0x7; pub const RISCV_BR_BGEU: u8 = 0x7;
const RISCV_LD_LB: u8 = 0x0; pub const RISCV_LD_LB: u8 = 0x0;
const RISCV_LD_LH: u8 = 0x1; pub const RISCV_LD_LH: u8 = 0x1;
const RISCV_LD_LW: u8 = 0x2; pub const RISCV_LD_LW: u8 = 0x2;
const RISCV_LD_LD: u8 = 0x3; pub const RISCV_LD_LD: u8 = 0x3;
const RISCV_LD_LBU: u8 = 0x4; pub const RISCV_LD_LBU: u8 = 0x4;
const RISCV_LD_LHU: u8 = 0x5; pub const RISCV_LD_LHU: u8 = 0x5;
const RISCV_LD_LWU: u8 = 0x6; pub const RISCV_LD_LWU: u8 = 0x6;
const RISCV_ST_STB: u8 = 0x0; pub const RISCV_ST_STH: u8 = 0x1;
const RISCV_ST_STH: u8 = 0x1; pub const RISCV_ST_STW: u8 = 0x2;
const RISCV_ST_STW: u8 = 0x2; pub const RISCV_ST_STB: u8 = 0x0;
const RISCV_ST_STD: u8 = 0x3; pub const RISCV_ST_STD: u8 = 0x3;
const RISCV_OPI_ADDI: u8 = 0x0; pub const RISCV_OPI_ADDI: u8 = 0x0;
const RISCV_OPI_SLTI: u8 = 0x2; pub const RISCV_OPI_SLTI: u8 = 0x2;
const RISCV_OPI_SLTIU: u8 = 0x3; pub const RISCV_OPI_SLTIU: u8 = 0x3;
const RISCV_OPI_XORI: u8 = 0x4; pub const RISCV_OPI_XORI: u8 = 0x4;
const RISCV_OPI_ORI: u8 = 0x6; pub const RISCV_OPI_ORI: u8 = 0x6;
const RISCV_OPI_ANDI: u8 = 0x7; pub const RISCV_OPI_ANDI: u8 = 0x7;
const RISCV_OPI_SLLI: u8 = 0x1; pub const RISCV_OPI_SLLI: u8 = 0x1;
const RISCV_OPI_SRI: u8 = 0x5; pub const RISCV_OPI_SRI: u8 = 0x5;
const RISCV_OPI_SRI_SRAI: u8 = 0x20; pub const RISCV_OPI_SRI_SRAI: u8 = 0x20;
const RISCV_OPI_SRI_SRLI: u8 = 0x0; pub const RISCV_OPI_SRI_SRLI: u8 = 0x0;
const RISCV_OP_ADD: u8 = 0x0; pub const RISCV_OP_ADD: u8 = 0x0;
const RISCV_OP_SLL: u8 = 0x1; pub const RISCV_OP_SLL: u8 = 0x1;
const RISCV_OP_SLT: u8 = 0x2; pub const RISCV_OP_SLT: u8 = 0x2;
const RISCV_OP_SLTU: u8 = 0x3; pub const RISCV_OP_SLTU: u8 = 0x3;
const RISCV_OP_XOR: u8 = 0x4; pub const RISCV_OP_XOR: u8 = 0x4;
const RISCV_OP_SR: u8 = 0x5; pub const RISCV_OP_SR: u8 = 0x5;
const RISCV_OP_OR: u8 = 0x6; pub const RISCV_OP_OR: u8 = 0x6;
const RISCV_OP_AND: u8 = 0x7; pub const RISCV_OP_AND: u8 = 0x7;
const RISCV_OP_ADD_ADD: u8 = 0x0; pub const RISCV_OP_ADD_ADD: u8 = 0x0;
const RISCV_OP_ADD_SUB: u8 = 0x20; pub const RISCV_OP_ADD_SUB: u8 = 0x20;
const RISCV_OP_SR_SRL: u8 = 0x0; pub const RISCV_OP_SR_SRL: u8 = 0x0;
const RISCV_OP_SR_SRA: u8 = 0x20; pub const RISCV_OP_SR_SRA: u8 = 0x20;
const RISCV_SYSTEM: u8 = 0x73; pub const RISCV_SYSTEM: u8 = 0x73;
const RISCV_OPIW_ADDIW: u8 = 0x0; pub const RISCV_OPIW_ADDIW: u8 = 0x0;
const RISCV_OPIW_SLLIW: u8 = 0x1; pub const RISCV_OPIW_SLLIW: u8 = 0x1;
const RISCV_OPIW_SRW: u8 = 0x5; pub const RISCV_OPIW_SRW: u8 = 0x5;
const RISCV_OPIW_SRW_SRLIW: u8 = 0x0; pub const RISCV_OPIW_SRW_SRLIW: u8 = 0x0;
const RISCV_OPIW_SRW_SRAIW: u8 = 0x20; pub const RISCV_OPIW_SRW_SRAIW: u8 = 0x20;
const RISCV_OPW_ADDSUBW: u8 = 0x0; pub const RISCV_OPW_ADDSUBW: u8 = 0x0;
const RISCV_OPW_SLLW: u8 = 0x1; pub const RISCV_OPW_SLLW: u8 = 0x1;
const RISCV_OPW_SRW: u8 = 0x5; pub const RISCV_OPW_SRW: u8 = 0x5;
const RISCV_OPW_ADDSUBW_ADDW: u8 = 0x0; pub const RISCV_OPW_ADDSUBW_ADDW: u8 = 0x0;
const RISCV_OPW_ADDSUBW_SUBW: u8 = 0x20; pub const RISCV_OPW_ADDSUBW_SUBW: u8 = 0x20;
const RISCV_OPW_SRW_SRLW: u8 = 0x0; pub const RISCV_OPW_SRW_SRLW: u8 = 0x0;
const RISCV_OPW_SRW_SRAW: u8 = 0x20; pub const RISCV_OPW_SRW_SRAW: u8 = 0x20;
const RISCV_SYSTEM_ENV: u8 = 0x0; pub const RISCV_SYSTEM_ENV: u8 = 0x0;
const RISCV_SYSTEM_ENV_ECALL: u8 = 0x0; pub const RISCV_SYSTEM_ENV_ECALL: u8 = 0x0;
const RISCV_SYSTEM_ENV_EBREAK: u8 = 0x1; pub const RISCV_SYSTEM_ENV_EBREAK: u8 = 0x1;
const RISCV_SYSTEM_CSRRS: u8 = 0x2; pub const RISCV_SYSTEM_CSRRS: u8 = 0x2;
const RISCV_SYSTEM_CSRRW: u8 = 0x1; pub const RISCV_SYSTEM_CSRRW: u8 = 0x1;
const RISCV_SYSTEM_CSRRC: u8 = 0x3; pub const RISCV_SYSTEM_CSRRC: u8 = 0x3;
const RISCV_SYSTEM_CSRRWI: u8 = 0x5; pub const RISCV_SYSTEM_CSRRWI: u8 = 0x5;
const RISCV_SYSTEM_CSRRSI: u8 = 0x6; pub const RISCV_SYSTEM_CSRRSI: u8 = 0x6;
const RISCV_SYSTEM_CSRRCI: u8 = 0x7; pub const RISCV_SYSTEM_CSRRCI: u8 = 0x7;
const RISCV_FLW: u8 = 0x07; pub const RISCV_FLW: u8 = 0x07;
const RISCV_FSW: u8 = 0x27; pub const RISCV_FSW: u8 = 0x27;
const RISCV_FMADD: u8 = 0x43; pub const RISCV_FMADD: u8 = 0x43;
const RISCV_FMSUB: u8 = 0x47; pub const RISCV_FMSUB: u8 = 0x47;
const RISCV_FNMSUB: u8 = 0x4b; pub const RISCV_FNMSUB: u8 = 0x4b;
const RISCV_FNMADD: u8 = 0x4f; pub const RISCV_FNMADD: u8 = 0x4f;
const RISCV_FP: u8 = 0x53; pub const RISCV_FP: u8 = 0x53;
const RISCV_FP_ADD: u8 = 0x0; pub const RISCV_FP_ADD: u8 = 0x0;
const RISCV_FP_SUB: u8 = 0x4; pub const RISCV_FP_SUB: u8 = 0x4;
const RISCV_FP_MUL: u8 = 0x8; pub const RISCV_FP_MUL: u8 = 0x8;
const RISCV_FP_DIV: u8 = 0xc; pub const RISCV_FP_DIV: u8 = 0xc;
const RISCV_FP_SQRT: u8 = 0x2c; pub const RISCV_FP_SQRT: u8 = 0x2c;
const RISCV_FP_FSGN: u8 = 0x10; pub const RISCV_FP_FSGN: u8 = 0x10;
const RISCV_FP_MINMAX: u8 = 0x14; pub const RISCV_FP_MINMAX: u8 = 0x14;
const RISCV_FP_FCVTW: u8 = 0x60; pub const RISCV_FP_FCVTW: u8 = 0x60;
const RISCV_FP_FMVXFCLASS: u8 = 0x70; pub const RISCV_FP_FMVXFCLASS: u8 = 0x70;
const RISCV_FP_FCMP: u8 = 0x50; pub const RISCV_FP_FCMP: u8 = 0x50;
const RISCV_FP_FEQS: u8 = 0x53; pub const RISCV_FP_FEQS: u8 = 0x53;
const RISCV_FP_FCVTS: u8 = 0x68; pub const RISCV_FP_FCVTS: u8 = 0x68;
const RISCV_FP_FCVTDS: u8 = 0x21; pub const RISCV_FP_FCVTDS: u8 = 0x21;
const RISCV_FP_FSGN_J: u8 = 0x0; pub const RISCV_FP_FSGN_J: u8 = 0x0;
const RISCV_FP_FSGN_JN: u8 = 0x1; pub const RISCV_FP_FSGN_JN: u8 = 0x1;
const RISCV_FP_FSGN_JX: u8 = 0x2; pub const RISCV_FP_FSGN_JX: u8 = 0x2;
const RISCV_FP_MINMAX_MIN: u8 = 0x0; pub const RISCV_FP_MINMAX_MIN: u8 = 0x0;
const RISCV_FP_MINMAX_MAX: u8 = 0x1; pub const RISCV_FP_MINMAX_MAX: u8 = 0x1;
const RISCV_FP_FCVTW_W: u8 = 0x0; pub const RISCV_FP_FCVTW_W: u8 = 0x0;
const RISCV_FP_FCVTW_WU: u8 = 0x1; pub const RISCV_FP_FCVTW_WU: u8 = 0x1;
const RISCV_FP_FCVTS_W: u8 = 0x0; pub const RISCV_FP_FCVTS_W: u8 = 0x0;
const RISCV_FP_FCVTS_WU: u8 = 0x1; pub const RISCV_FP_FCVTS_WU: u8 = 0x1;
const RISCV_FP_FMVXFCLASS_FMVX: u8 = 0x0; pub const RISCV_FP_FMVXFCLASS_FMVX: u8 = 0x0;
const RISCV_FP_FMVXFCLASS_FCLASS: u8 = 0x1; pub const RISCV_FP_FMVXFCLASS_FCLASS: u8 = 0x1;
const RISCV_FP_FCMP_FEQ: u8 = 2; pub const RISCV_FP_FCMP_FEQ: u8 = 2;
const RISCV_FP_FCMP_FLT: u8 = 1; pub const RISCV_FP_FCMP_FLT: u8 = 1;
const RISCV_FP_FCMP_FLE: u8 = 0; pub const RISCV_FP_FCMP_FLE: u8 = 0;
const RISCV_FP_FMVW: u8 = 0x78; pub const RISCV_FP_FMVW: u8 = 0x78;
const names_op: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"]; const names_op: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"];