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RISC OP MUL and DIV + changement prototype OneInstruction

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This commit is contained in:
Moysan Gabriel 2022-11-16 17:48:55 +01:00
parent 98f4c0b67e
commit a4230cd357
1 changed files with 84 additions and 40 deletions
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124
src/machine.rs
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@ -31,6 +31,15 @@ impl Machine {
let mut unsigned_reg1 : u64 = 0; let mut unsigned_reg1 : u64 = 0;
let mut unsigned_reg2 : u64 = 0; let mut unsigned_reg2 : u64 = 0;
let mut long_result : i128 = 0;
/*__int128 longResult;
int32_t localDataa, localDatab;
int64_t localLongResult;
uint32_t localDataaUnsigned, localDatabUnsigned;
int32_t localResult;
float localFloat;
uint64_t value;*/
if machine.instructions.len() <= machine.pc as usize { if machine.instructions.len() <= machine.pc as usize {
println!("ERROR : number max of instructions rushed"); println!("ERROR : number max of instructions rushed");
@ -79,49 +88,84 @@ impl Machine {
}, },
RISCV_OP => { RISCV_OP => {
match inst.funct3 { if(inst.funct7 == 1){
RISCV_OP_ADD => { match inst.funct3 {
// RISCV_OP_ADD_ADD inaccessible RISCV_OP_M_MUL => {
/*if (inst.funct7 == RISCV_OP_ADD_ADD) { long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128;
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];*/ machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as u32;
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize]; },
//} RISCV_OP_M_MULH => {
}, long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128;
RISCV_OP_SLL => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f); },
}, RISCV_OP_M_MULHSU => {
RISCV_OP_SLT => { unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { long_result = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128;
machine.int_reg[inst.rd as usize] = 1; machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as u32;
} else { },
machine.int_reg[inst.rd as usize] = 0; // VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve
/*
* VOIR SI LES CAST machine.int_reg[....] = i128*u64 as u32 FAUSSE RESULTAT (suit pas la logique du code c++)
* WHAT DA HECK
*/
RISCV_OP_M_MULHU => {
unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
long_result = (unsigned_reg1 * unsigned_reg2) as i128;
machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as u32;
},
RISCV_OP_M_DIV => {
machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize]);
} }
}, _ => {
RISCV_OP_SLTU => { println!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n");
unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
if unsigned_reg1 < unsigned_reg2 {
machine.int_reg[inst.rd as usize] = 1;
} else {
machine.int_reg[inst.rd as usize] = 0;
} }
},
RISCV_OP_XOR => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ machine.int_reg[inst.rs2 as usize];
},
RISCV_OP_SR => {
// RISCV_OP_SR_SRL inaccessible
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> (machine.int_reg[inst.rs2 as usize] & 0x3f);
},
RISCV_OP_OR => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | machine.int_reg[inst.rs2 as usize];
},
RISCV_OP_AND => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize];
},
_ => {
println!("RISCV_OP undefined case\n");
} }
} else {
match inst.funct3 {
RISCV_OP_ADD => {
// RISCV_OP_ADD_ADD inaccessible
/*if (inst.funct7 == RISCV_OP_ADD_ADD) {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];*/
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize];
//}
},
RISCV_OP_SLL => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f);
},
RISCV_OP_SLT => {
if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
machine.int_reg[inst.rd as usize] = 1;
} else {
machine.int_reg[inst.rd as usize] = 0;
}
},
RISCV_OP_SLTU => {
unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
if unsigned_reg1 < unsigned_reg2 {
machine.int_reg[inst.rd as usize] = 1;
} else {
machine.int_reg[inst.rd as usize] = 0;
}
},
RISCV_OP_XOR => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ machine.int_reg[inst.rs2 as usize];
},
RISCV_OP_SR => {
// RISCV_OP_SR_SRL inaccessible
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> (machine.int_reg[inst.rs2 as usize] & 0x3f);
},
RISCV_OP_OR => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | machine.int_reg[inst.rs2 as usize];
},
RISCV_OP_AND => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize];
},
_ => {
println!("RISCV_OP undefined case\n");
}
}//LA
} }
} }
_ => { println!("{} opcode non géré", inst.opcode)}, _ => { println!("{} opcode non géré", inst.opcode)},