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Merge branch 'decode_print' of gitlab.istic.univ-rennes1.fr:simpleos/burritos into decode_print

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Baptiste 2023-02-01 17:13:23 +01:00
commit ab182436a4
1 changed files with 70 additions and 37 deletions
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53
src/simulator/print.rs
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@ -13,7 +13,7 @@ const NAMES_OPW: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""];
const NAMES_OPIW: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""];
// Register name mapping
const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1", // fp ou s0 ?
const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", // fp ou s0 ?
"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
"s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
"t3", "t4", "t5", "t6"];
@ -81,15 +81,7 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
}
},
RISCV_JALR => {
if ins.rd == 0 {
if ins.rs1 == 1 {
"ret".to_string()
} else {
format!("jr\t{:X}", ins.imm31_12)
}
} else {
format!("jalr\t{}, ({})", ins.imm12_I_signed, REG_X[rs1])
}
format!("jalr\t{},{}({})", REG_X[rd], ins.imm12_I_signed, REG_X[rs1])
},
RISCV_BR => {
format!("{}\t{}, {}, {}", NAMES_BR[ins.funct3 as usize], REG_X[rs1], REG_X[rs2], ins.imm13_signed)
@ -250,4 +242,45 @@ mod test {
assert_eq!("beq\ta7, a6, 0", print::print(beq, 0));
}
#[test]
fn test_small_program() {
/* Code for :
int a = 0;
int b = 5;
a = b;
a = a * b;
a = a + b;
b = a - b;
*/
assert_eq!("addi sp,sp,-32", print::print(decode::decode(0xfe010113), 0));
assert_eq!("sd s0,24(sp)", print::print(decode::decode(0x00813c23), 0));
assert_eq!("addi s0,sp,32", print::print(decode::decode(0x02010413), 0));
assert_eq!("sw zero,-20(s0)", print::print(decode::decode(0xfe042623), 0));
assert_eq!("addi a5,zero,5", print::print(decode::decode(0x00500793), 0));
assert_eq!("sw a5,-24(s0)", print::print(decode::decode(0xfef42423), 0));
assert_eq!("lw a5,-24(s0)", print::print(decode::decode(0xfe842783), 0));
assert_eq!("sw a5,-20(s0)", print::print(decode::decode(0xfef42623), 0));
assert_eq!("lw a5,-20(s0)", print::print(decode::decode(0xfec42783), 0));
assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0));
assert_eq!("lw a5,-24(s0)", print::print(decode::decode(0xfe842783), 0));
//assert_eq!("mulw a5,a4,a5", print::print(decode::decode(0x02f707bb), 0));
assert_eq!("sw a5,-20(s0)", print::print(decode::decode(0xfef42623), 0));
assert_eq!("lw a5,-20(s0)", print::print(decode::decode(0xfec42783), 0));
assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0));
assert_eq!("lw a5,-24(s0)", print::print(decode::decode(0xfe842783), 0));
assert_eq!("addw a5,a4,a5", print::print(decode::decode(0x00f707bb), 0));
assert_eq!("sw a5,-20(s0)", print::print(decode::decode(0xfef42623), 0));
assert_eq!("lw a5,-20(s0)", print::print(decode::decode(0xfec42783), 0));
assert_eq!("addi a4,a5,0", print::print(decode::decode(0x00078713), 0));
assert_eq!("lw a5,-24(s0)", print::print(decode::decode(0xfe842783), 0));
assert_eq!("subw a5,a4,a5", print::print(decode::decode(0x40f707bb), 0));
assert_eq!("sw a5,-24(s0)", print::print(decode::decode(0xfef42423), 0));
assert_eq!("addi a5,zero,0", print::print(decode::decode(0x00000793), 0));
assert_eq!("addi a0,a5,0", print::print(decode::decode(0x00078513), 0));
assert_eq!("ld s0,24(sp)", print::print(decode::decode(0x01813403), 0));
assert_eq!("addi sp,sp,32", print::print(decode::decode(0x02010113), 0));
assert_eq!("jalr zero,0(ra)", print::print(decode::decode(0x00008067), 0));
}
}