quentinlegot/burritos
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'decode_print' of gitlab.istic.univ-rennes1.fr:simpleos/burritos into decode_print

Browse Source
This commit is contained in:
Baptiste 2022-11-16 18:01:08 +01:00
commit adf7f0a02e
2 changed files with 160 additions and 103 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

124
src/machine.rs
View File

@ -41,6 +41,15 @@ impl Machine {
let mut unsigned_reg1 : u64 = 0; let mut unsigned_reg1 : u64 = 0;
let mut unsigned_reg2 : u64 = 0; let mut unsigned_reg2 : u64 = 0;
let mut long_result : i128 = 0;
/*__int128 longResult;
int32_t localDataa, localDatab;
int64_t localLongResult;
uint32_t localDataaUnsigned, localDatabUnsigned;
int32_t localResult;
float localFloat;
uint64_t value;*/
if machine.instructions.len() <= machine.pc as usize { if machine.instructions.len() <= machine.pc as usize {
println!("ERROR : number max of instructions rushed"); println!("ERROR : number max of instructions rushed");
@ -96,49 +105,84 @@ impl Machine {
}, },
RISCV_OP => { RISCV_OP => {
match inst.funct3 { if(inst.funct7 == 1){
RISCV_OP_ADD => { match inst.funct3 {
// RISCV_OP_ADD_ADD inaccessible RISCV_OP_M_MUL => {
/*if (inst.funct7 == RISCV_OP_ADD_ADD) { long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128;
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];*/ machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as u32;
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize]; },
//} RISCV_OP_M_MULH => {
}, long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128;
RISCV_OP_SLL => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f); },
}, RISCV_OP_M_MULHSU => {
RISCV_OP_SLT => { unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { long_result = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128;
machine.int_reg[inst.rd as usize] = 1; machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as u32;
} else { },
machine.int_reg[inst.rd as usize] = 0; // VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve
/*
* VOIR SI LES CAST machine.int_reg[....] = i128*u64 as u32 FAUSSE RESULTAT (suit pas la logique du code c++)
* WHAT DA HECK
*/
RISCV_OP_M_MULHU => {
unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
long_result = (unsigned_reg1 * unsigned_reg2) as i128;
machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as u32;
},
RISCV_OP_M_DIV => {
machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize]);
} }
}, _ => {
RISCV_OP_SLTU => { println!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n");
unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
if unsigned_reg1 < unsigned_reg2 {
machine.int_reg[inst.rd as usize] = 1;
} else {
machine.int_reg[inst.rd as usize] = 0;
} }
},
RISCV_OP_XOR => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ machine.int_reg[inst.rs2 as usize];
},
RISCV_OP_SR => {
// RISCV_OP_SR_SRL inaccessible
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> (machine.int_reg[inst.rs2 as usize] & 0x3f);
},
RISCV_OP_OR => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | machine.int_reg[inst.rs2 as usize];
},
RISCV_OP_AND => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize];
},
_ => {
println!("RISCV_OP undefined case\n");
} }
} else {
match inst.funct3 {
RISCV_OP_ADD => {
// RISCV_OP_ADD_ADD inaccessible
/*if (inst.funct7 == RISCV_OP_ADD_ADD) {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];*/
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize];
//}
},
RISCV_OP_SLL => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f);
},
RISCV_OP_SLT => {
if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
machine.int_reg[inst.rd as usize] = 1;
} else {
machine.int_reg[inst.rd as usize] = 0;
}
},
RISCV_OP_SLTU => {
unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
if unsigned_reg1 < unsigned_reg2 {
machine.int_reg[inst.rd as usize] = 1;
} else {
machine.int_reg[inst.rd as usize] = 0;
}
},
RISCV_OP_XOR => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ machine.int_reg[inst.rs2 as usize];
},
RISCV_OP_SR => {
// RISCV_OP_SR_SRL inaccessible
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> (machine.int_reg[inst.rs2 as usize] & 0x3f);
},
RISCV_OP_OR => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | machine.int_reg[inst.rs2 as usize];
},
RISCV_OP_AND => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize];
},
_ => {
println!("RISCV_OP undefined case\n");
}
}//LA
} }
}, },
//****************************************************************************************** //******************************************************************************************

137
src/print.rs
View File

@ -170,11 +170,24 @@ const names_br: [&str; 8] = ["beq", "bne", "", "", "blt", "bge", "bltu", "bgeu"]
const names_st: [&str; 4] = ["sb", "sh", "sw", "sd"]; const names_st: [&str; 4] = ["sb", "sh", "sw", "sd"];
const names_ld: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"]; const names_ld: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"];
const names_opw: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""]; const names_opw: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""];
const names_opiw: [&str; 8] = ["addwi", "sllwi", "", "", "", "sri", "", ""]; const names_opiw: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""];
// Register name mapping
const reg_x: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1", // fp ou s0 ?
"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
"s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
"t3", "t4", "t5", "t6"];
const _reg_f: [&str; 32] = ["ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1",
"fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7",
"fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11",
"ft8", "ft9", "ft10", "ft11"];
pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
let rd = ins.rd as usize;
let rs1 = ins.rs1 as usize;
let rs2 = ins.rs2 as usize;
match ins.opcode { match ins.opcode {
RISCV_OP => { RISCV_OP => {
@ -200,33 +213,33 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
name = names_op[ins.funct3 as usize]; name = names_op[ins.funct3 as usize];
} }
} }
format!("{} r{}, r{}, r{}", name.to_string(), &ins.rd.to_string(), &ins.rs1.to_string(), &ins.rs2.to_string()) format!("{}\t{}, {}, {}", name.to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2])
}, },
RISCV_OPI => { RISCV_OPI => {
// SHAMT OR IMM // SHAMT OR IMM
if ins.funct3 == RISCV_OPI_SRI { if ins.funct3 == RISCV_OPI_SRI {
if ins.funct7 == RISCV_OPI_SRI_SRLI { if ins.funct7 == RISCV_OPI_SRI_SRLI {
format!("slrii x{}, x{}, {}", ins.rd.to_string(), ins.rs1.to_string(), ins.shamt.to_string()) format!("slrii\t{}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string())
} else { } else {
format!("srai x{}, x{}, {}", ins.rd.to_string(), ins.rs1.to_string(), ins.shamt.to_string()) format!("srai\t{}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string())
} }
} else if ins.funct3 == RISCV_OPI_SLLI { } else if ins.funct3 == RISCV_OPI_SLLI {
format!("{} x{}, x{}, {}", names_opi[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.shamt.to_string()) format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.shamt.to_string())
} else { } else {
format!("{} x{}, x{}, {}", names_opi[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.imm12_I_signed.to_string()) format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string())
} }
}, },
RISCV_LUI => { RISCV_LUI => {
format!("lui x{}, 0x{:X}", ins.rd.to_string(), ins.imm31_12) format!("lui\t{}, 0x{:X}", reg_x[rd], ins.imm31_12)
}, },
RISCV_AUIPC => { RISCV_AUIPC => {
format!("auipc x{}, {:X}", ins.rd.to_string(), ins.imm31_12) format!("auipc\t{}, {:X}", reg_x[rd], ins.imm31_12)
}, },
RISCV_JAL => { RISCV_JAL => {
if ins.rd == 0 { if ins.rd == 0 {
format!("j {}", ins.imm31_12.to_string()) format!("j\t{}", ins.imm31_12.to_string())
} else { } else {
format!("jal x{}, {:X}", ins.rd.to_string(), (pc - 4 + ins.imm21_1_signed)) format!("jal\t{}, {:X}", reg_x[rd], (pc - 4 + ins.imm21_1_signed))
} }
}, },
RISCV_JALR => { RISCV_JALR => {
@ -234,52 +247,52 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
if ins.rs1 == 1 { if ins.rs1 == 1 {
"ret".to_string() "ret".to_string()
} else { } else {
format!("jr {:X}", ins.imm31_12) format!("jr\t{:X}", ins.imm31_12)
} }
} else { } else {
format!("jalr {}, (r{})", ins.imm12_I_signed.to_string(), ins.rs1.to_string()) format!("jalr\t{}, ({})", ins.imm12_I_signed.to_string(), reg_x[rs1])
} }
}, },
RISCV_BR => { RISCV_BR => {
format!("{} r{} x{} {}", names_br[ins.funct3 as usize].to_string(), ins.rs1.to_string(), ins.rs2.to_string(), ins.imm13_signed.to_string()) format!("{}\t{}, {}, {}", names_br[ins.funct3 as usize].to_string(), reg_x[rs1], reg_x[rs2], ins.imm13_signed.to_string())
}, },
RISCV_LD => { RISCV_LD => {
format!("{} x{}, {}(x{})", names_ld[ins.funct3 as usize].to_string(), ins.rd.to_string(), ins.imm12_I_signed.to_string(), ins.rs1.to_string()) format!("{}\t{}, {}({})", names_ld[ins.funct3 as usize].to_string(), reg_x[rd], ins.imm12_I_signed.to_string(), reg_x[rs1])
}, },
RISCV_ST => { RISCV_ST => {
format!("{} x{}, {}(x{})", names_st[ins.funct3 as usize].to_string(), ins.rs2.to_string(), ins.imm12_S_signed.to_string(), ins.rs1.to_string()) format!("{}\t{}, {}({})", names_st[ins.funct3 as usize].to_string(), reg_x[rs2], ins.imm12_S_signed.to_string(), reg_x[rs1])
}, },
RISCV_OPIW => { RISCV_OPIW => {
if ins.funct3 == RISCV_OPIW_SRW { if ins.funct3 == RISCV_OPIW_SRW {
if ins.funct7 == RISCV_OPIW_SRW_SRLIW { if ins.funct7 == RISCV_OPIW_SRW_SRLIW {
format!("srlwi x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) format!("srlwi\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
} else { } else {
format!("srawi x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) format!("srawi\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
} }
} else if ins.funct3 == RISCV_OPIW_SLLIW { } else if ins.funct3 == RISCV_OPIW_SLLIW {
format!("{} x{}, x{}, x{}", names_opi[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2])
} else { } else {
format!("{} x{}, x{}, x{}", names_opiw[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.imm12_I_signed.to_string()) format!("{}\t{}, {}, {}", names_opiw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string())
} }
}, },
RISCV_OPW => { RISCV_OPW => {
if ins.funct7 == 1 { if ins.funct7 == 1 {
format!("{}w x{}, x{}, x{}", names_mul[ins.funct3 as usize].to_string(), ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) format!("{}w\t{}, {}, {}", names_mul[ins.funct3 as usize].to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2])
} else { } else {
if ins.funct3 == RISCV_OP_ADD { if ins.funct3 == RISCV_OP_ADD {
if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW { if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW {
format!("addw x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) format!("addw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
} else { } else {
format!("subw x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) format!("subw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
} }
} else if ins.funct3 == RISCV_OPW_SRW { } else if ins.funct3 == RISCV_OPW_SRW {
if ins.funct7 == RISCV_OPW_SRW_SRLW { if ins.funct7 == RISCV_OPW_SRW_SRLW {
format!("srlw x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) format!("srlw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
} else { } else {
format!("sraw x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) format!("sraw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
} }
} else { } else {
format!("{} x{}, x{}, x{}", names_opw[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string()) format!("{}\t{}, {}, {}", names_opw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2])
} }
} }
}, },
@ -305,11 +318,11 @@ mod test {
let slr = decode::decode(0b0000000_10000_10001_101_11100_0110011); let slr = decode::decode(0b0000000_10000_10001_101_11100_0110011);
let sra = decode::decode(0b0100000_10000_10001_101_11100_0110011); let sra = decode::decode(0b0100000_10000_10001_101_11100_0110011);
assert_eq!("sub r28, r17, r16", print::print(sub, 0)); assert_eq!("sub\tt3, a7, a6", print::print(sub, 0));
assert_eq!("xor r28, r17, r16", print::print(xor, 0)); assert_eq!("xor\tt3, a7, a6", print::print(xor, 0));
assert_eq!("srl r28, r17, r16", print::print(slr, 0)); assert_eq!("srl\tt3, a7, a6", print::print(slr, 0));
assert_eq!("sra r28, r17, r16", print::print(sra, 0)); assert_eq!("sra\tt3, a7, a6", print::print(sra, 0));
assert_eq!("add r28, r17, r16", print::print(add, 0)); assert_eq!("add\tt3, a7, a6", print::print(add, 0));
} }
@ -322,21 +335,21 @@ mod test {
let xori = decode::decode(0b_0000000000010001_100_11100_0010011); let xori = decode::decode(0b_0000000000010001_100_11100_0010011);
let ori = decode::decode(0b00000000000_10001_110_11100_0010011); let ori = decode::decode(0b00000000000_10001_110_11100_0010011);
let andi = decode::decode(0b000000000000_10001_111_11100_0010011); let andi = decode::decode(0b000000000000_10001_111_11100_0010011);
assert_eq!("andi x28, x17, 0", print::print(andi, 0)); assert_eq!("andi\tt3, a7, 0", print::print(andi, 0));
assert_eq!("addi x28, x17, 0", print::print(addi, 0)); assert_eq!("addi\tt3, a7, 0", print::print(addi, 0));
assert_eq!("slli x28, x17, 0", print::print(slli, 0)); assert_eq!("slli\tt3, a7, 0", print::print(slli, 0));
assert_eq!("slti x28, x17, 0", print::print(slti, 0)); assert_eq!("slti\tt3, a7, 0", print::print(slti, 0));
assert_eq!("sltiu x28, x17, 0", print::print(sltiu, 0)); assert_eq!("sltiu\tt3, a7, 0", print::print(sltiu, 0));
assert_eq!("xori x28, x17, 0", print::print(xori, 0)); assert_eq!("xori\tt3, a7, 0", print::print(xori, 0));
assert_eq!("ori x28, x17, 0", print::print(ori, 0)); assert_eq!("ori\tt3, a7, 0", print::print(ori, 0));
} }
#[test] #[test]
fn test_lui() { fn test_lui() {
let lui = decode::decode(0b01110001000011111000_11100_0110111); let lui = decode::decode(0b01110001000011111000_11100_0110111);
let lui_negatif = decode::decode(0b11110001000011111000_11100_0110111); let lui_negatif = decode::decode(0b11110001000011111000_11100_0110111);
assert_eq!("lui x28, 0x710F8000", print::print(lui, 0)); assert_eq!("lui\tt3, 0x710F8000", print::print(lui, 0));
assert_eq!("lui x28, 0xF10F8000", print::print(lui_negatif, 0)); assert_eq!("lui\tt3, 0xF10F8000", print::print(lui_negatif, 0));
} }
#[test] #[test]
@ -349,14 +362,14 @@ mod test {
let lhu = decode::decode(0b010111110000_10001_101_11100_0000011); let lhu = decode::decode(0b010111110000_10001_101_11100_0000011);
let ld = decode::decode(0b010111110000_10001_011_11100_0000011); let ld = decode::decode(0b010111110000_10001_011_11100_0000011);
let lwu = decode::decode(0b010111110000_10001_110_11100_0000011); let lwu = decode::decode(0b010111110000_10001_110_11100_0000011);
// TODO: imm négatif produit une erreur
assert_eq!("lb x28, 1520(x17)", print::print(lb, 0)); assert_eq!("lb\tt3, 1520(a7)", print::print(lb, 0));
assert_eq!("lh x28, 1520(x17)", print::print(lh, 0)); assert_eq!("lh\tt3, 1520(a7)", print::print(lh, 0));
assert_eq!("lw x28, 1520(x17)", print::print(lw, 0)); assert_eq!("lw\tt3, 1520(a7)", print::print(lw, 0));
assert_eq!("lbu x28, 1520(x17)", print::print(lbu, 0)); assert_eq!("lbu\tt3, 1520(a7)", print::print(lbu, 0));
assert_eq!("lhu x28, 1520(x17)", print::print(lhu, 0)); assert_eq!("lhu\tt3, 1520(a7)", print::print(lhu, 0));
assert_eq!("ld x28, 1520(x17)", print::print(ld, 0)); assert_eq!("ld\tt3, 1520(a7)", print::print(ld, 0));
assert_eq!("lwu x28, 1520(x17)", print::print(lwu, 0)); assert_eq!("lwu\tt3, 1520(a7)", print::print(lwu, 0));
} }
#[test] #[test]
@ -366,20 +379,20 @@ mod test {
let srlw: decode::Instruction = decode::decode(0b0000000_10000_10001_101_11100_0111011); let srlw: decode::Instruction = decode::decode(0b0000000_10000_10001_101_11100_0111011);
let sraw: decode::Instruction = decode::decode(0b0100000_10000_10001_101_11100_0111011); let sraw: decode::Instruction = decode::decode(0b0100000_10000_10001_101_11100_0111011);
assert_eq!("addw x28, x17, x16", print::print(addw, 0)); assert_eq!("addw\tt3, a7, a6", print::print(addw, 0));
assert_eq!("sllw x28, x17, x16", print::print(sllw, 0)); assert_eq!("sllw\tt3, a7, a6", print::print(sllw, 0));
assert_eq!("srlw x28, x17, x16", print::print(srlw, 0)); assert_eq!("srlw\tt3, a7, a6", print::print(srlw, 0));
assert_eq!("sraw x28, x17, x16", print::print(sraw, 0)); assert_eq!("sraw\tt3, a7, a6", print::print(sraw, 0));
} }
#[test] #[test]
fn test_opwi() { fn test_opwi() {
let addwi: decode::Instruction =decode::decode(0b000000000000_10001_000_11100_0011011); let addiw: decode::Instruction =decode::decode(0b000000000000_10001_000_11100_0011011);
let sllwi: decode::Instruction = decode::decode(0b0000000_10000_10001_001_11100_0011011); let slliw: decode::Instruction = decode::decode(0b0000000_10000_10001_001_11100_0011011);
let srai: decode::Instruction = decode::decode(0b010000010001_10001_101_11100_0010011); let srai: decode::Instruction = decode::decode(0b010000010001_10001_101_11100_0010011);
assert_eq!("addwi x28, x17, x0", print::print(addwi, 0)); assert_eq!("addiw\tt3, a7, 0", print::print(addiw, 0));
assert_eq!("slli x28, x17, x16", print::print(sllwi, 0)); assert_eq!("slli\tt3, a7, a6", print::print(slliw, 0));
assert_eq!("srai x28, x17, 17", print::print(srai, 0)); assert_eq!("srai\tt3, a7, 17", print::print(srai, 0));
} }
@ -391,12 +404,12 @@ mod test {
let bge: decode::Instruction = decode::decode(0b0000000_10000_10001_101_00000_1100011); let bge: decode::Instruction = decode::decode(0b0000000_10000_10001_101_00000_1100011);
let bltu: decode::Instruction = decode::decode(0b0000000_10000_10001_110_00000_1100011); let bltu: decode::Instruction = decode::decode(0b0000000_10000_10001_110_00000_1100011);
let bgeu: decode::Instruction = decode::decode(0b0000000_10000_10001_111_00000_1100011); let bgeu: decode::Instruction = decode::decode(0b0000000_10000_10001_111_00000_1100011);
assert_eq!("blt r17 x16 0", print::print(blt, 0)); assert_eq!("blt\ta7, a6, 0", print::print(blt, 0));
assert_eq!("bge r17 x16 0", print::print(bge, 0)); assert_eq!("bge\ta7, a6, 0", print::print(bge, 0));
assert_eq!("bltu r17 x16 0", print::print(bltu, 0)); assert_eq!("bltu\ta7, a6, 0", print::print(bltu, 0));
assert_eq!("bgeu r17 x16 0", print::print(bgeu, 0)); assert_eq!("bgeu\ta7, a6, 0", print::print(bgeu, 0));
assert_eq!("bne r17 x16 0", print::print(bne, 0)); assert_eq!("bne\ta7, a6, 0", print::print(bne, 0));
assert_eq!("beq r17 x16 0", print::print(beq, 0)); assert_eq!("beq\ta7, a6, 0", print::print(beq, 0));
} }
} }