Merge branch 'decode_print' of gitlab.istic.univ-rennes1.fr:simpleos/burritos into decode_print

src/simulator/machine.rs

@@ -1,8 +1,61 @@
+use std::ops::{Add, Sub};
+
 use super::{decode::{Instruction, decode}};
 use super::global::*;
 /// doit disparaitre
 const MEM_SIZE : usize = 4096;
 
+trait RegisterNum: Add<Output=Self> + Sub<Output=Self> + PartialEq + Copy {}
+
+impl RegisterNum for i64 {}
+
+impl RegisterNum for f32 {}
+
+struct Register<U: RegisterNum> {
+	register: [U; 32]
+}
+
+impl<U: RegisterNum> Register<U> {
+
+	pub fn get_reg(&self, position: usize) -> U {
+		self.register[position]
+	}
+
+}
+
+impl Register<i64> {
+
+	pub fn init() -> Register<i64> {
+		Register { 
+			register: [0i64; 32]
+		}
+	}
+
+	pub fn set_reg(&mut self, position: usize, value: i64) {
+		if position != 0 {
+			self.register[position] = value;
+		} else {
+			// Panic ou rien ? (dans le doute pour le moment panic)
+			unreachable!("You can't write to zero register")
+		}
+	}
+
+}
+
+impl Register<f32> {
+
+	pub fn init() -> Register<f32> {
+		Register { 
+			register: [0f32; 32]
+		}
+	}
+
+	pub fn set_reg(&mut self, position: usize, value: f32) {
+		self.register[position] = value;
+	}
+
+}
+
 pub struct Machine {
 	pub pc : u64,
 	pub int_reg : [i64 ; 32],
@@ -26,13 +79,17 @@ impl Machine {
 			value >>= 1;
 		}
 
+		// let int_reg = Register::<i64>::init();
+		// let fp_reg = Register::<f32>::init();
+
 		Machine {
 			pc : 0,
 			instructions : [0 ; 100],
 			int_reg : [0 ; 32],
 			main_memory : [0 ; MEM_SIZE],
 			shiftmask
-		}	
+		}
+		
 	}
 
 	/// Read from main memory of the machine