From fe2fe40a758307434a7701119867c26238a65293 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Wed, 11 Jan 2023 15:31:52 +0100 Subject: [PATCH 1/3] Cleaned up cargo clippy warnings on print.rs --- src/simulator/print.rs | 116 ++++++++++++++++++++--------------------- 1 file changed, 57 insertions(+), 59 deletions(-) diff --git a/src/simulator/print.rs b/src/simulator/print.rs index 99ce2d0..47cb58a 100644 --- a/src/simulator/print.rs +++ b/src/simulator/print.rs @@ -163,22 +163,22 @@ pub const RISCV_ATOM_MINU: u8 = 0x18; pub const RISCV_ATOM_MAXU: u8 = 0x1c; -const names_op: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"]; -const names_opi: [&str; 8] = ["addi", "slli", "slti", "sltiu", "xori", "slri", "ori", "andi"]; -const names_mul: [&str; 8] = ["mpylo", "mpyhi", "mpyhi", "mpyhi", "divhi", "divhi", "divlo", "divlo"]; -const names_br: [&str; 8] = ["beq", "bne", "", "", "blt", "bge", "bltu", "bgeu"]; -const names_st: [&str; 4] = ["sb", "sh", "sw", "sd"]; -const names_ld: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"]; -const names_opw: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""]; -const names_opiw: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""]; +const NAMES_OP: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"]; +const NAMES_OPI: [&str; 8] = ["addi", "slli", "slti", "sltiu", "xori", "slri", "ori", "andi"]; +const NAMES_MUL: [&str; 8] = ["mpylo", "mpyhi", "mpyhi", "mpyhi", "divhi", "divhi", "divlo", "divlo"]; +const NAMES_BR: [&str; 8] = ["beq", "bne", "", "", "blt", "bge", "bltu", "bgeu"]; +const NAMES_ST: [&str; 4] = ["sb", "sh", "sw", "sd"]; +const NAMES_LD: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"]; +const NAMES_OPW: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""]; +const NAMES_OPIW: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""]; // Register name mapping -const reg_x: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1", // fp ou s0 ? +const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1", // fp ou s0 ? "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"]; -const _reg_f: [&str; 32] = ["ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1", +const REG_F: [&str; 32] = ["ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"]; @@ -193,53 +193,51 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 RISCV_OP => { let name: &str; if ins.funct7 == 1 { // Use mul array - name = names_mul[ins.funct3 as usize] - } else { - if ins.funct3 == RISCV_OP_ADD { - // Add or Sub - if ins.funct7 == RISCV_OP_ADD_ADD { - name = "add"; - } else { - name = "sub"; - } - } else if ins.funct3 == RISCV_OP_SR { - // Srl or Sra - if ins.funct7 == RISCV_OP_SR_SRL { - name = "srl"; - } else { - name = "sra"; - } + name = NAMES_MUL[ins.funct3 as usize] + } else if ins.funct3 == RISCV_OP_ADD { + // Add or Sub + if ins.funct7 == RISCV_OP_ADD_ADD { + name = "add"; } else { - name = names_op[ins.funct3 as usize]; + name = "sub"; } + } else if ins.funct3 == RISCV_OP_SR { + // Srl or Sra + if ins.funct7 == RISCV_OP_SR_SRL { + name = "srl"; + } else { + name = "sra"; + } + } else { + name = NAMES_OP[ins.funct3 as usize]; } - format!("{}\t{}, {}, {}", name.to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("{}\t{}, {}, {}", name, REG_X[rd], REG_X[rs1], REG_X[rs2]) }, RISCV_OPI => { // SHAMT OR IMM if ins.funct3 == RISCV_OPI_SRI { if ins.funct7 == RISCV_OPI_SRI_SRLI { - format!("slrii\t{}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string()) + format!("slrii\t{}, {}, {}", REG_X[rd], REG_X[rs1], ins.shamt) } else { - format!("srai\t{}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string()) + format!("srai\t{}, {}, {}", REG_X[rd], REG_X[rs1], ins.shamt) } } else if ins.funct3 == RISCV_OPI_SLLI { - format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.shamt.to_string()) + format!("{}\t{}, {}, {}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.shamt) } else { - format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string()) + format!("{}\t{}, {}, {}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed) } }, RISCV_LUI => { - format!("lui\t{}, 0x{:X}", reg_x[rd], ins.imm31_12) + format!("lui\t{}, 0x{:X}", REG_X[rd], ins.imm31_12) }, RISCV_AUIPC => { - format!("auipc\t{}, {:X}", reg_x[rd], ins.imm31_12) + format!("auipc\t{}, {:X}", REG_X[rd], ins.imm31_12) }, RISCV_JAL => { if ins.rd == 0 { - format!("j\t{}", ins.imm31_12.to_string()) + format!("j\t{}", ins.imm31_12) } else { - format!("jal\t{}, {:X}", reg_x[rd], (pc - 4 + ins.imm21_1_signed)) + format!("jal\t{}, {:X}", REG_X[rd], (pc - 4 + ins.imm21_1_signed)) } }, RISCV_JALR => { @@ -250,50 +248,48 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 format!("jr\t{:X}", ins.imm31_12) } } else { - format!("jalr\t{}, ({})", ins.imm12_I_signed.to_string(), reg_x[rs1]) + format!("jalr\t{}, ({})", ins.imm12_I_signed, REG_X[rs1]) } }, RISCV_BR => { - format!("{}\t{}, {}, {}", names_br[ins.funct3 as usize].to_string(), reg_x[rs1], reg_x[rs2], ins.imm13_signed.to_string()) + format!("{}\t{}, {}, {}", NAMES_BR[ins.funct3 as usize], REG_X[rs1], REG_X[rs2], ins.imm13_signed) }, RISCV_LD => { - format!("{}\t{}, {}({})", names_ld[ins.funct3 as usize].to_string(), reg_x[rd], ins.imm12_I_signed.to_string(), reg_x[rs1]) + format!("{}\t{}, {}({})", NAMES_LD[ins.funct3 as usize], REG_X[rd], ins.imm12_I_signed, REG_X[rs1]) }, RISCV_ST => { - format!("{}\t{}, {}({})", names_st[ins.funct3 as usize].to_string(), reg_x[rs2], ins.imm12_S_signed.to_string(), reg_x[rs1]) + format!("{}\t{}, {}({})", NAMES_ST[ins.funct3 as usize], REG_X[rs2], ins.imm12_S_signed, REG_X[rs1]) }, RISCV_OPIW => { if ins.funct3 == RISCV_OPIW_SRW { if ins.funct7 == RISCV_OPIW_SRW_SRLIW { - format!("srlwi\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("srlwi\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) } else { - format!("srawi\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("srawi\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) } } else if ins.funct3 == RISCV_OPIW_SLLIW { - format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("{}\t{}, {}, {}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) } else { - format!("{}\t{}, {}, {}", names_opiw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string()) + format!("{}\t{}, {}, {}", NAMES_OPIW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed) } }, RISCV_OPW => { if ins.funct7 == 1 { - format!("{}w\t{}, {}, {}", names_mul[ins.funct3 as usize].to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2]) - } else { - if ins.funct3 == RISCV_OP_ADD { - if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW { - format!("addw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) - } else { - format!("subw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) - } - } else if ins.funct3 == RISCV_OPW_SRW { - if ins.funct7 == RISCV_OPW_SRW_SRLW { - format!("srlw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) - } else { - format!("sraw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2]) - } + format!("{}w\t{}, {}, {}", NAMES_MUL[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) + } else if ins.funct3 == RISCV_OP_ADD { + if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW { + format!("addw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) } else { - format!("{}\t{}, {}, {}", names_opw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2]) + format!("subw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) } + } else if ins.funct3 == RISCV_OPW_SRW { + if ins.funct7 == RISCV_OPW_SRW_SRLW { + format!("srlw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) + } else { + format!("sraw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2]) + } + } else { + format!("{}\t{}, {}, {}", NAMES_OPW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2]) } }, RISCV_SYSTEM => { @@ -307,6 +303,8 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64 #[cfg(test)] mod test { + + #![allow(clippy::unusual_byte_groupings)] use crate::simulator::{decode, print}; From 5c375633229a3930d49c1fc6cd75f266b84d5ce3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Wed, 11 Jan 2023 15:34:12 +0100 Subject: [PATCH 2/3] =?UTF-8?q?=F0=9F=9A=A8=20Cleaned=20up=20clippy=20warn?= =?UTF-8?q?ings=20for=20machine.rs?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/simulator/machine.rs | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 57f4550..57fd15e 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -23,7 +23,7 @@ impl Machine { value = (value << 32) + value; for item in &mut shiftmask { *item = value; - value = value >> 1; + value >>= 1; } Machine { @@ -202,8 +202,7 @@ impl Machine { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64; }, RISCV_OPI_SLTI => { - machine.int_reg[inst.rd as usize] = - if machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as i64 { 1 } else { 0 }; + machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as i64) as i64; }, RISCV_OPI_XORI => { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as i64; @@ -378,6 +377,5 @@ impl Machine { #[cfg(test)] mod test { - use super::Machine; } From ee8762fdb84667aa12fb030a37632e1506218073 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 11 Jan 2023 15:34:51 +0100 Subject: [PATCH 3/3] read_memory now panic instead of just displaying the error and continue the execution --- src/simulator/machine.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 57f4550..d63ea1e 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -44,7 +44,7 @@ impl Machine { /// - **address** in the memory to read pub fn read_memory(machine : &mut Machine, size : i32, address : usize) -> u64 { if size != 1 && size != 2 && size != 4 && size != 8 { - println!("ERROR read_memory : wrong size parameter {}, must be (1, 2, 4 or 8)", size); + panic!("ERROR read_memory : wrong size parameter {}, must be (1, 2, 4 or 8)", size); } let mut ret : u64 = machine.main_memory[address] as u64; @@ -379,5 +379,5 @@ impl Machine { #[cfg(test)] mod test { use super::Machine; - + }