From c74c99499eaf3b17b83efd6148bebdb6548e0bb7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Fri, 24 Mar 2023 17:32:04 +0100 Subject: [PATCH] :recycle: Removed loads of casts to usize --- src/simulator/machine.rs | 152 +++++++++++++++++++-------------------- 1 file changed, 76 insertions(+), 76 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index a2c8046..2cc98ad 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -53,8 +53,8 @@ pub struct Register { impl Register { - pub fn get_reg(&self, position: usize) -> U { - self.register[position] + pub fn get_reg(&self, position: u8) -> U { + self.register[position as usize] } } @@ -203,11 +203,11 @@ impl Machine { /// - **machine** the machine to get the status from pub fn print_machine_status(machine: &mut Machine) { println!("######### Machine status #########"); - for i in (0..32).step_by(3) { - print!(">{0: <4} : {1:<16x} ", print::REG_X[i], machine.int_reg.get_reg(i)); - print!(">{0: <4} : {1:<16x} ", print::REG_X[i+1], machine.int_reg.get_reg(i+1)); + for i in (0..32 as usize).step_by(3) { + print!(">{0: <4} : {1:<16x} ", print::REG_X[i], machine.int_reg.get_reg(i as u8)); + print!(">{0: <4} : {1:<16x} ", print::REG_X[i+1], machine.int_reg.get_reg((i+1) as u8)); if i+2 < 32 { - print!(">{0: <4} : {1:<16x} ", print::REG_X[i+2], machine.int_reg.get_reg(i+2)); + print!(">{0: <4} : {1:<16x} ", print::REG_X[i+2], machine.int_reg.get_reg((i+2) as u8)); } println!(); } @@ -283,7 +283,7 @@ impl Machine { }, RISCV_JALR => { let tmp = machine.pc; - machine.pc = (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as u64 & 0xfffffffe; + machine.pc = (machine.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64) as u64 & 0xfffffffe; machine.int_reg.set_reg(inst.rd as usize, tmp as i64); Ok(()) }, @@ -328,32 +328,32 @@ impl Machine { fn branch_instruction(machine: &mut Machine, inst: Instruction) -> Result<(), MachineError> { match inst.funct3 { RISCV_BR_BEQ => { - if machine.int_reg.get_reg(inst.rs1 as usize) == machine.int_reg.get_reg(inst.rs2 as usize) { + if machine.int_reg.get_reg(inst.rs1) == machine.int_reg.get_reg(inst.rs2) { machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64; } }, RISCV_BR_BNE => { - if machine.int_reg.get_reg(inst.rs1 as usize) != machine.int_reg.get_reg(inst.rs2 as usize) { + if machine.int_reg.get_reg(inst.rs1) != machine.int_reg.get_reg(inst.rs2) { machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64; } }, RISCV_BR_BLT => { - if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) { + if machine.int_reg.get_reg(inst.rs1) < machine.int_reg.get_reg(inst.rs2) { machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64; } }, RISCV_BR_BGE => { - if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) { + if machine.int_reg.get_reg(inst.rs1) >= machine.int_reg.get_reg(inst.rs2) { machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64; } }, RISCV_BR_BLTU => { - if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) { + if machine.int_reg.get_reg(inst.rs1) < machine.int_reg.get_reg(inst.rs2) { machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64; } }, RISCV_BR_BGEU => { - if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) { + if machine.int_reg.get_reg(inst.rs1) >= machine.int_reg.get_reg(inst.rs2) { machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64; } }, @@ -368,19 +368,19 @@ impl Machine { fn load_instruction(machine: &mut Machine, inst: Instruction) -> Result<(), MachineError> { match inst.funct3 { RISCV_LD_LB | RISCV_LD_LBU => { - let tmp = Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64; + let tmp = Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64) as usize) as i64; machine.int_reg.set_reg(inst.rd as usize, tmp); }, RISCV_LD_LH | RISCV_LD_LHU => { - let tmp = Self::read_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64; + let tmp = Self::read_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64) as usize) as i64; machine.int_reg.set_reg(inst.rd as usize, tmp); }, RISCV_LD_LW | RISCV_LD_LWU => { - let tmp = Self::read_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64; + let tmp = Self::read_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64) as usize) as i64; machine.int_reg.set_reg(inst.rd as usize, tmp); }, RISCV_LD_LD => { - let tmp = Self::read_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64; + let tmp = Self::read_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64) as usize) as i64; machine.int_reg.set_reg(inst.rd as usize, tmp); }, _ => panic!("In LD switch case, this should never happen... Instr was {}", inst.value) @@ -391,10 +391,10 @@ impl Machine { /// Executes RISC-V Store Instructions on the machine fn store_instruction(machine: &mut Machine, inst: Instruction) -> Result<(), MachineError> { match inst.funct3 { - RISCV_ST_STB => Self::write_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64), - RISCV_ST_STH => Self::write_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64), - RISCV_ST_STW => Self::write_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64), - RISCV_ST_STD => Self::write_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64), + RISCV_ST_STB => Self::write_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2) as u64), + RISCV_ST_STH => Self::write_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2) as u64), + RISCV_ST_STW => Self::write_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2) as u64), + RISCV_ST_STD => Self::write_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2) as u64), _ => panic!("In ST switch case, this should never happen... Instr was {}", inst.value) } Ok(()) @@ -403,16 +403,16 @@ impl Machine { /// Executes RISC-V Integer Register-Immediate Instructions on the machine fn opi_instruction(machine: &mut Machine, inst: Instruction) -> Result<(), MachineError> { match inst.funct3 { - RISCV_OPI_ADDI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64), - RISCV_OPI_SLTI => machine.int_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1 as usize) < inst.imm12_I_signed as i64) as i64), - RISCV_OPI_XORI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) ^ inst.imm12_I_signed as i64), - RISCV_OPI_ORI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) | inst.imm12_I_signed as i64), - RISCV_OPI_ANDI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) & inst.imm12_I_signed as i64), - RISCV_OPI_SLLI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) << inst.shamt), + RISCV_OPI_ADDI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64), + RISCV_OPI_SLTI => machine.int_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1) < inst.imm12_I_signed as i64) as i64), + RISCV_OPI_XORI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) ^ inst.imm12_I_signed as i64), + RISCV_OPI_ORI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) | inst.imm12_I_signed as i64), + RISCV_OPI_ANDI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) & inst.imm12_I_signed as i64), + RISCV_OPI_SLLI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) << inst.shamt), RISCV_OPI_SRI => if inst.funct7_smaller == RISCV_OPI_SRI_SRLI { - machine.int_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1 as usize) >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64); + machine.int_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1) >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64); } else { // SRAI - machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) >> inst.shamt); + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) >> inst.shamt); }, _ => panic!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value) } @@ -427,53 +427,53 @@ impl Machine { if inst.funct7 == 1 { match inst.funct3 { RISCV_OP_M_MUL => { - long_result = (machine.int_reg.get_reg(inst.rs1 as usize) * machine.int_reg.get_reg(inst.rs2 as usize)) as i128; + long_result = (machine.int_reg.get_reg(inst.rs1) * machine.int_reg.get_reg(inst.rs2)) as i128; machine.int_reg.set_reg(inst.rd as usize, (long_result & 0xffffffffffffffff) as i64) }, RISCV_OP_M_MULH => { - long_result = (machine.int_reg.get_reg(inst.rs1 as usize) * machine.int_reg.get_reg(inst.rs2 as usize)) as i128; + long_result = (machine.int_reg.get_reg(inst.rs1) * machine.int_reg.get_reg(inst.rs2)) as i128; machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64) }, RISCV_OP_M_MULHSU => { - unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64; - long_result = (machine.int_reg.get_reg(inst.rs1 as usize) as u64 * unsigned_reg2) as i128; + unsigned_reg2 = machine.int_reg.get_reg(inst.rs2) as u64; + long_result = (machine.int_reg.get_reg(inst.rs1) as u64 * unsigned_reg2) as i128; machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64) }, RISCV_OP_M_MULHU => { - unsigned_reg1 = machine.int_reg.get_reg(inst.rs1 as usize) as u64; - unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64; + unsigned_reg1 = machine.int_reg.get_reg(inst.rs1) as u64; + unsigned_reg2 = machine.int_reg.get_reg(inst.rs2) as u64; long_result = (unsigned_reg1 * unsigned_reg2) as i128; machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64); }, - RISCV_OP_M_DIV => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) / machine.int_reg.get_reg(inst.rs2 as usize)), + RISCV_OP_M_DIV => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) / machine.int_reg.get_reg(inst.rs2)), _ => panic!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n") } } else { match inst.funct3 { RISCV_OP_ADD => if inst.funct7 == RISCV_OP_ADD_ADD { - machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) + machine.int_reg.get_reg(inst.rs2 as usize)) + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) + machine.int_reg.get_reg(inst.rs2)) } else { - machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) - machine.int_reg.get_reg(inst.rs2 as usize)) + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) - machine.int_reg.get_reg(inst.rs2)) }, - RISCV_OP_SLL => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) << (machine.int_reg.get_reg(inst.rs2 as usize) & 0x3f)), - RISCV_OP_SLT => if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) { + RISCV_OP_SLL => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) << (machine.int_reg.get_reg(inst.rs2) & 0x3f)), + RISCV_OP_SLT => if machine.int_reg.get_reg(inst.rs1) < machine.int_reg.get_reg(inst.rs2) { machine.int_reg.set_reg(inst.rd as usize, 1) } else { machine.int_reg.set_reg(inst.rd as usize, 0) }, RISCV_OP_SLTU => { - unsigned_reg1 = machine.int_reg.get_reg(inst.rs1 as usize) as u64; - unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64; + unsigned_reg1 = machine.int_reg.get_reg(inst.rs1) as u64; + unsigned_reg2 = machine.int_reg.get_reg(inst.rs2) as u64; if unsigned_reg1 < unsigned_reg2 { machine.int_reg.set_reg(inst.rd as usize, 1) } else { machine.int_reg.set_reg(inst.rd as usize, 0) } }, - RISCV_OP_XOR => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) ^ machine.int_reg.get_reg(inst.rs2 as usize)), - RISCV_OP_SR => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) >> machine.int_reg.get_reg(inst.rs2 as usize)), // RISCV_OP_SR_SRL inaccessible - RISCV_OP_OR => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) | machine.int_reg.get_reg(inst.rs2 as usize)), - RISCV_OP_AND => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) & machine.int_reg.get_reg(inst.rs2 as usize)), + RISCV_OP_XOR => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) ^ machine.int_reg.get_reg(inst.rs2)), + RISCV_OP_SR => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) >> machine.int_reg.get_reg(inst.rs2)), // RISCV_OP_SR_SRL inaccessible + RISCV_OP_OR => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) | machine.int_reg.get_reg(inst.rs2)), + RISCV_OP_AND => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) & machine.int_reg.get_reg(inst.rs2)), _ => panic!("RISCV_OP undefined case\n") } } @@ -482,7 +482,7 @@ impl Machine { /// Exectutes simple RISC-V *iw instructions on the machine fn opiw_instruction(machine: &mut Machine, inst: Instruction) -> Result<(), MachineError> { - let local_data = machine.int_reg.get_reg(inst.rs1 as usize); + let local_data = machine.int_reg.get_reg(inst.rs1); match inst.funct3 { RISCV_OPIW_ADDIW => { let result = local_data + inst.imm12_I_signed as i64; @@ -508,10 +508,10 @@ impl Machine { /// Executes simple RISC-V *w instructions on the machine fn opw_instruction(machine: &mut Machine, inst: Instruction) -> Result<(), MachineError> { if inst.funct7 == 1 { // rv64m - let local_data_a = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff; - let local_data_b = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff; - let local_data_a_unsigned = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff; - let local_data_b_unsigned = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff; + let local_data_a = machine.int_reg.get_reg(inst.rs1) & 0xffffffff; + let local_data_b = machine.int_reg.get_reg(inst.rs2) & 0xffffffff; + let local_data_a_unsigned = machine.int_reg.get_reg(inst.rs1) & 0xffffffff; + let local_data_b_unsigned = machine.int_reg.get_reg(inst.rs2) & 0xffffffff; // Match case for multiplication operations (in standard extension RV32M) match inst.funct3 { @@ -523,8 +523,8 @@ impl Machine { _ => panic!("this instruction ({}) doesn't exists", inst.value) } } else { // others rv64 OPW operations - let local_dataa = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff; - let local_datab = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff; + let local_dataa = machine.int_reg.get_reg(inst.rs1) & 0xffffffff; + let local_datab = machine.int_reg.get_reg(inst.rs2) & 0xffffffff; // Match case for base OP operation match inst.funct3 { RISCV_OPW_ADDSUBW => if inst.funct7 == RISCV_OPW_ADDSUBW_ADDW { @@ -547,26 +547,26 @@ impl Machine { /// Executes simple RISC-V floating point instructions on the machine fn fp_instruction(machine: &mut Machine, inst: Instruction) -> Result<(), MachineError> { match inst.funct7 { - RISCV_FP_ADD => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) + machine.fp_reg.get_reg(inst.rs2 as usize)), - RISCV_FP_SUB => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) - machine.fp_reg.get_reg(inst.rs2 as usize)), - RISCV_FP_MUL => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) * machine.fp_reg.get_reg(inst.rs2 as usize)), - RISCV_FP_DIV => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) / machine.fp_reg.get_reg(inst.rs2 as usize)), - RISCV_FP_SQRT => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize).sqrt()), + RISCV_FP_ADD => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1) + machine.fp_reg.get_reg(inst.rs2)), + RISCV_FP_SUB => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1) - machine.fp_reg.get_reg(inst.rs2)), + RISCV_FP_MUL => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1) * machine.fp_reg.get_reg(inst.rs2)), + RISCV_FP_DIV => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1) / machine.fp_reg.get_reg(inst.rs2)), + RISCV_FP_SQRT => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1).sqrt()), RISCV_FP_FSGN => { - let local_float = machine.fp_reg.get_reg(inst.rs1 as usize); + let local_float = machine.fp_reg.get_reg(inst.rs1); match inst.funct3 { - RISCV_FP_FSGN_J => if machine.fp_reg.get_reg(inst.rs2 as usize) < 0f32 { + RISCV_FP_FSGN_J => if machine.fp_reg.get_reg(inst.rs2) < 0f32 { machine.fp_reg.set_reg(inst.rd as usize, -local_float) } else { machine.fp_reg.set_reg(inst.rd as usize, local_float) }, - RISCV_FP_FSGN_JN => if machine.fp_reg.get_reg(inst.rs2 as usize) < 0f32 { + RISCV_FP_FSGN_JN => if machine.fp_reg.get_reg(inst.rs2) < 0f32 { machine.fp_reg.set_reg(inst.rd as usize, local_float) } else { machine.fp_reg.set_reg(inst.rd as usize, -local_float) }, - RISCV_FP_FSGN_JX => if (machine.fp_reg.get_reg(inst.rs2 as usize) < 0.0 && machine.fp_reg.get_reg(inst.rs1 as usize) >= 0.0) || - (machine.fp_reg.get_reg(inst.rs2 as usize) >= 0.0 && machine.fp_reg.get_reg(inst.rs1 as usize) < 0.0) { + RISCV_FP_FSGN_JX => if (machine.fp_reg.get_reg(inst.rs2) < 0.0 && machine.fp_reg.get_reg(inst.rs1) >= 0.0) || + (machine.fp_reg.get_reg(inst.rs2) >= 0.0 && machine.fp_reg.get_reg(inst.rs1) < 0.0) { machine.fp_reg.set_reg(inst.rd as usize, -local_float) } else { machine.fp_reg.set_reg(inst.rd as usize, local_float) @@ -575,8 +575,8 @@ impl Machine { } }, RISCV_FP_MINMAX => { - let r1 = machine.fp_reg.get_reg(inst.rs1 as usize); - let r2 = machine.fp_reg.get_reg(inst.rs2 as usize); + let r1 = machine.fp_reg.get_reg(inst.rs1); + let r2 = machine.fp_reg.get_reg(inst.rs2); match inst.funct3 { RISCV_FP_MINMAX_MIN => machine.fp_reg.set_reg(inst.rd as usize, if r1 < r2 {r1} else {r2}), RISCV_FP_MINMAX_MAX => machine.fp_reg.set_reg(inst.rd as usize, if r1 > r2 {r1} else {r2}), @@ -585,31 +585,31 @@ impl Machine { }, RISCV_FP_FCVTW => { if inst.rs2 == RISCV_FP_FCVTW_W { - machine.int_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) as i64) + machine.int_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1) as i64) } else { - machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1 as usize) as u64) as i64) + machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1) as u64) as i64) } }, RISCV_FP_FCVTS => { if inst.rs2 == RISCV_FP_FCVTS_W { - machine.fp_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) as f32); + machine.fp_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) as f32); } else { - machine.fp_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1 as usize) as u32) as f32); + machine.fp_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1) as u32) as f32); } }, - RISCV_FP_FMVW => machine.fp_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) as f32), + RISCV_FP_FMVW => machine.fp_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1) as f32), RISCV_FP_FMVXFCLASS => { if inst.funct3 == RISCV_FP_FMVXFCLASS_FMVX { - machine.int_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) as i64); + machine.int_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1) as i64); } else { panic!("Fclass instruction is not handled in riscv simulator"); } }, RISCV_FP_FCMP => { match inst.funct3 { - RISCV_FP_FCMP_FEQ => machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1 as usize) == machine.fp_reg.get_reg(inst.rs2 as usize)) as i64), - RISCV_FP_FCMP_FLT => machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1 as usize) < machine.fp_reg.get_reg(inst.rs2 as usize)) as i64), - RISCV_FP_FCMP_FLE => machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1 as usize) <= machine.fp_reg.get_reg(inst.rs2 as usize)) as i64), + RISCV_FP_FCMP_FEQ => machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1) == machine.fp_reg.get_reg(inst.rs2)) as i64), + RISCV_FP_FCMP_FLT => machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1) < machine.fp_reg.get_reg(inst.rs2)) as i64), + RISCV_FP_FCMP_FLE => machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1) <= machine.fp_reg.get_reg(inst.rs2)) as i64), _ => panic!("this instruction ({}) doesn't exists", inst.value) } }, @@ -633,12 +633,12 @@ impl Machine { /// Get value from int register pub fn read_int_register(&self, index: usize) -> i64 { - self.int_reg.get_reg(index) + self.int_reg.get_reg(index as u8) } /// Get value from float register pub fn read_fp_register(&self, index: usize) -> f32 { - self.fp_reg.get_reg(index) + self.fp_reg.get_reg(index as u8) } /// Write into int register