From 069a8e57414ac63fe2b9d75103f70db3a7124701 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 1 Feb 2023 16:39:40 +0100 Subject: [PATCH 1/6] Using a struct for registers instead of an array --- src/simulator/machine.rs | 72 +++++++++++++++++----------------------- src/simulator/mod.rs | 2 +- 2 files changed, 31 insertions(+), 43 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index e336842..45bafe7 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -58,7 +58,7 @@ impl Register { pub struct Machine { pub pc : u64, - pub int_reg : [i64 ; 32], + pub int_reg : Register, pub instructions : [u64 ; 100], pub main_memory : [u8 ; MEM_SIZE], pub shiftmask : [u64 ; 64] @@ -85,7 +85,7 @@ impl Machine { Machine { pc : 0, instructions : [0 ; 100], - int_reg : [0 ; 32], + int_reg : Register::::init(), main_memory : [0 ; MEM_SIZE], shiftmask } @@ -175,19 +175,19 @@ impl Machine { match inst.opcode { RISCV_LUI => { - machine.int_reg[inst.rd as usize] = inst.imm31_12 as i64; + machine.int_reg.set_reg(inst.rd as usize, inst.imm31_12 as i64); }, RISCV_AUIPC => { - machine.int_reg[inst.rd as usize] = machine.pc as i64 - 4 + inst.imm31_12 as i64; + machine.int_reg.set_reg(inst.rd as usize,machine.pc as i64 - 4 + inst.imm31_12 as i64); }, RISCV_JAL => { - machine.int_reg[inst.rd as usize] = machine.pc as i64; + machine.int_reg.set_reg(inst.rd as usize, machine.pc as i64); machine.pc += inst.imm21_1_signed as u64 - 4; }, RISCV_JALR => { let tmp = machine.pc; - machine.pc = (machine.int_reg[inst.rs1 as usize] as u64 + inst.imm12_I_signed as u64) & 0xfffffffe; - machine.int_reg[inst.rd as usize] = tmp as i64; + machine.pc = (machine.int_reg.get_reg(inst.rs1 as usize) as u64 + inst.imm12_I_signed as u64) & 0xfffffffe; + machine.int_reg.set_reg(inst.rd as usize, tmp as i64); }, //****************************************************************************************** @@ -195,32 +195,32 @@ impl Machine { RISCV_BR => { match inst.funct3 { RISCV_BR_BEQ => { - if machine.int_reg[inst.rs1 as usize] == machine.int_reg[inst.rs2 as usize] { + if machine.int_reg.get_reg(inst.rs1 as usize) == machine.int_reg.get_reg(inst.rs2 as usize) { machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BNE => { - if machine.int_reg[inst.rs1 as usize] != machine.int_reg[inst.rs2 as usize] { + if machine.int_reg.get_reg(inst.rs1 as usize) != machine.int_reg.get_reg(inst.rs2 as usize) { machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BLT => { - if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { + if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) { machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BGE => { - if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] { + if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) { machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BLTU => { - if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { + if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) { machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BGEU => { - if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] { + if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) { machine.pc += inst.imm13_signed as u64 - 4; } }, @@ -234,49 +234,37 @@ impl Machine { // Treatment for: LOAD INSTRUCTIONS RISCV_LD => { match inst.funct3 { - RISCV_LD_LB => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; + RISCV_LD_LB | RISCV_LD_LBU => { + machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); }, - RISCV_LD_LH => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; + RISCV_LD_LH | RISCV_LD_LHU => { + machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); }, - RISCV_LD_LW => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; + RISCV_LD_LW | RISCV_LD_LWU => { + machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); }, RISCV_LD_LD => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 8, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; - }, - - // same thing three opration ? - RISCV_LD_LBU => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; - }, - RISCV_LD_LHU => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; - }, - RISCV_LD_LWU => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; + machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); }, _ => { panic!("In LD switch case, this should never happen... Instr was {}", inst.value); } } }, - // store instructions RISCV_ST => { match inst.funct3 { RISCV_ST_STB => { - Self::write_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); // Possible bugs à cause du cast ici + Self::write_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64); }, RISCV_ST_STH => { - Self::write_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); + Self::write_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64); }, RISCV_ST_STW => { - Self::write_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); + Self::write_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64); }, RISCV_ST_STD => { - Self::write_memory(machine, 8, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); + Self::write_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64); }, _ => { panic!("In ST switch case, this should never happen... Instr was {}", inst.value); @@ -288,22 +276,22 @@ impl Machine { RISCV_OPI => { match inst.funct3 { RISCV_OPI_ADDI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64); }, RISCV_OPI_SLTI => { - machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as i64) as i64; + machine.int_reg.set_reg(inst.rd as usize, if machine.int_reg.get_reg(inst.rs1 as usize) < inst.imm12_I_signed as i64 { 1 } else { 0 } ); }, RISCV_OPI_XORI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as i64; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) ^ inst.imm12_I_signed as i64); }, RISCV_OPI_ORI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | inst.imm12_I_signed as i64; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) | inst.imm12_I_signed as i64); }, RISCV_OPI_ANDI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & inst.imm12_I_signed as i64; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) & inst.imm12_I_signed as i64); }, RISCV_OPI_SLLI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) << inst.shamt); }, RISCV_OPI_SRI => { if inst.funct7_smaller == RISCV_OPI_SRI_SRLI { diff --git a/src/simulator/mod.rs b/src/simulator/mod.rs index 6aef6be..266e97a 100644 --- a/src/simulator/mod.rs +++ b/src/simulator/mod.rs @@ -167,7 +167,7 @@ pub mod global { /// /// Store doubleword (SD) (64 bits) /// - /// `SD rs2, imm12(rs1` => `rs2 -> mem[rs1 + imm12]` + /// `SD rs2, imm12(rs1)` => `rs2 -> mem[rs1 + imm12]` pub const RISCV_ST_STD: u8 = 0x3; /// Type: I From ff0d10edb59aac31f48f3a0cdcc3fade2848f419 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 1 Feb 2023 16:41:49 +0100 Subject: [PATCH 2/6] add floating point instructions --- src/simulator/machine.rs | 108 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 83be4a4..4965234 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -398,6 +398,114 @@ impl Machine { } } } + }, + //****************************************************************************************** + // Treatment for: Simple floating point extension + RISCV_FP => { + match inst.funct7 { + RISCV_FP_ADD => { + machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] + machine.fp_reg[inst.rs2 as usize]; + }, + RISCV_FP_SUB => { + machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] - machine.fp_reg[inst.rs2 as usize]; + }, + RISCV_FP_MUL => { + machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] * machine.fp_reg[inst.rs2 as usize]; + }, + RISCV_FP_DIV => { + machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] / machine.fp_reg[inst.rs2 as usize]; + }, + RISCV_FP_SQRT => { + machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize].sqrt(); + }, + RISCV_FP_FSGN => { + let local_float = machine.fp_reg[inst.rs1 as usize]; + match inst.funct3 { + RISCV_FP_FSGN_J => { + if machine.fp_reg[inst.rs2 as usize] < 0 { + machine.fp_reg[inst.rd as usize] = -local_float; + } else { + machine.fp_reg[inst.rd as usize] = local_float; + } + } + RISCV_FP_FSGN_JN => { + if machine.fp_reg[inst.rs2 as usize] < 0 { + machine.fp_reg[inst.rd as usize] = local_float; + } else { + machine.fp_reg[inst.rd as usize] = -local_float; + } + } + RISCV_FP_FSGN_JX => { + if (machine.fp_reg[inst.rs2 as usize] < 0 && machine.fp_reg[inst.rs1 as usize] >= 0) || (machine.fp_reg[inst.rs2 as usize] >= 0 && machine.fp_reg[inst.rs1 as usize] < 0) { + machine.fp_reg[inst.rd as usize] = -local_float; + } else { + machine.fp_reg[inst.rd as usize] = local_float; + } + } + _ => { + panic!("this instruction ({}) doesn't exists", inst.value); + } + } + }, + RISCV_FP_MINMAX => { + let r1 = machine.fp_reg[inst.rs1 as usize]; + let r2 = machine.fp_reg[inst.rs2 as usize]; + match inst.funct3 { + RISCV_FP_MINMAX_MIN => { + machine.fp_reg[inst.rd as usize] = if r1 < r2 {r1} else {r2} + }, + RISCV_FP_MINMAX_MAX => { + machine.fp_reg[inst.rd as usize] = if r1 > r2 {r1} else {r2} + }, + _ => { + panic!("this instruction ({}) doesn't exists", inst.value); + } + } + }, + RISCV_FP_FCVTW => { + if inst.rs2 == RISCV_FP_FCVTW_W { + machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize]; + } else { + machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] as u64; + } + }, + RISCV_FP_FCVTS => { + if inst.rs2 == RISCV_FP_FCVTS_W { + machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize]; + } else { + machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] as u32; + } + }, + RISCV_FP_FMVW => { + machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize]; + }, + RISCV_FP_FMVXFCLASS => { + if inst.funct3 == RISCV_FP_FMVXFCLASS_FMVX { + machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize]; + } else { + panic!("Fclass instruction is not handled in riscv simulator"); + } + }, + RISCV_FP_FCMP => { + match inst.funct3 { + RISCV_FP_FCMP_FEQ => { + machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] == machine.fp_reg[inst.rs2 as usize] {1} else {0}; + }, + RISCV_FP_FCMP_FLT => { + machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] < machine.fp_reg[inst.rs2 as usize] {1} else {0}; + }, + RISCV_FP_FCMP_FLE => { + machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] <= machine.fp_reg[inst.rs2 as usize] {1} else {0}; + }, + _ => { + panic!("this instruction ({}) doesn't exists", inst.value); + } + } + }, + _ => { + panic!("this instruction ({}) doesn't exists", inst.value); + } + } } _ => { panic!("{} opcode non géré", inst.opcode)}, } From 1efcd73ae71da17fe1016ba03b3cdfe3e9d6d376 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 1 Feb 2023 17:02:19 +0100 Subject: [PATCH 3/6] OPW & OP for funct7 == -1 --- src/simulator/machine.rs | 60 ++++++++++++++++++++-------------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 45bafe7..ae9511e 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -342,42 +342,42 @@ impl Machine { match inst.funct3 { RISCV_OP_ADD => { if inst.funct7 == RISCV_OP_ADD_ADD { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize]; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) + machine.int_reg.get_reg(inst.rs2 as usize)); } else { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize]; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) - machine.int_reg.get_reg(inst.rs2 as usize)); } }, RISCV_OP_SLL => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f); + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) << (machine.int_reg.get_reg(inst.rs2 as usize) & 0x3f)); }, RISCV_OP_SLT => { - if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { - machine.int_reg[inst.rd as usize] = 1; + if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) { + machine.int_reg.set_reg(inst.rd as usize, 1); } else { - machine.int_reg[inst.rd as usize] = 0; + machine.int_reg.set_reg(inst.rd as usize, 0); } }, RISCV_OP_SLTU => { - unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64; - unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; + unsigned_reg1 = machine.int_reg.get_reg(inst.rs1 as usize) as u64; + unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64; if unsigned_reg1 < unsigned_reg2 { - machine.int_reg[inst.rd as usize] = 1; + machine.int_reg.set_reg(inst.rd as usize, 1); } else { - machine.int_reg[inst.rd as usize] = 0; + machine.int_reg.set_reg(inst.rd as usize, 0); } }, RISCV_OP_XOR => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ machine.int_reg[inst.rs2 as usize]; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) ^ machine.int_reg.get_reg(inst.rs2 as usize)); }, RISCV_OP_SR => { // RISCV_OP_SR_SRL inaccessible - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> (machine.int_reg[inst.rs2 as usize] & 0x3f); + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) >> machine.int_reg.get_reg(inst.rs2 as usize)); }, RISCV_OP_OR => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | machine.int_reg[inst.rs2 as usize]; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) | machine.int_reg.get_reg(inst.rs2 as usize)); }, RISCV_OP_AND => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize]; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) & machine.int_reg.get_reg(inst.rs2 as usize)); }, _ => { panic!("RISCV_OP undefined case\n"); @@ -389,53 +389,53 @@ impl Machine { // Treatment for: OPW INSTRUCTIONS RISCV_OPW => { if inst.funct7 == 1 { - let local_data_a = machine.int_reg[inst.rs1 as usize] & 0xffffffff; - let local_data_b = machine.int_reg[inst.rs2 as usize] & 0xffffffff; - let local_data_a_unsigned = machine.int_reg[inst.rs1 as usize] & 0xffffffff; - let local_data_b_unsigned = machine.int_reg[inst.rs2 as usize] & 0xffffffff; + let local_data_a = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff; + let local_data_b = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff; + let local_data_a_unsigned = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff; + let local_data_b_unsigned = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff; // Match case for multiplication operations (in standard extension RV32M) match inst.funct3 { RISCV_OPW_M_MULW => { - machine.int_reg[inst.rd as usize] = local_data_a * local_data_b; + machine.int_reg.set_reg(inst.rd as usize, local_data_a * local_data_b); }, RISCV_OPW_M_DIVW => { - machine.int_reg[inst.rd as usize] = local_data_a / local_data_b; + machine.int_reg.set_reg(inst.rd as usize, local_data_a / local_data_b); }, RISCV_OPW_M_DIVUW => { - machine.int_reg[inst.rd as usize] = local_data_a_unsigned / local_data_b_unsigned; + machine.int_reg.set_reg(inst.rd as usize, local_data_a_unsigned / local_data_b_unsigned); }, RISCV_OPW_M_REMW => { - machine.int_reg[inst.rd as usize] = local_data_a % local_data_b; + machine.int_reg.set_reg(inst.rd as usize, local_data_a % local_data_b); }, RISCV_OPW_M_REMUW => { - machine.int_reg[inst.rd as usize] = local_data_a_unsigned % local_data_b_unsigned; + machine.int_reg.set_reg(inst.rd as usize, local_data_a_unsigned % local_data_b_unsigned); }, _ => { panic!("this instruction ({}) doesn't exists", inst.value); } } } else { - let local_dataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff; - let local_datab = machine.int_reg[inst.rs2 as usize] & 0xffffffff; + let local_dataa = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff; + let local_datab = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff; // Match case for base OP operation match inst.funct3 { RISCV_OPW_ADDSUBW => { if inst.funct7 == RISCV_OPW_ADDSUBW_ADDW { - machine.int_reg[inst.rd as usize] = local_dataa + local_datab; + machine.int_reg.set_reg(inst.rd as usize, local_dataa + local_datab); } else { // SUBW - machine.int_reg[inst.rd as usize] = local_dataa - local_datab; + machine.int_reg.set_reg(inst.rd as usize, local_dataa - local_datab); } }, RISCV_OPW_SLLW => { - machine.int_reg[inst.rd as usize] = local_dataa << (local_datab & 0x1f); + machine.int_reg.set_reg(inst.rd as usize, local_dataa << (local_datab & 0x1f)); }, RISCV_OPW_SRW => { if inst.funct7 == RISCV_OPW_SRW_SRLW { - machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize] as i64; + machine.int_reg.set_reg(inst.rd as usize, local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize] as i64); } else { // SRAW - machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f); + machine.int_reg.set_reg(inst.rd as usize, local_dataa >> (local_datab & 0x1f)); } }, _ => { From 67ebff7ad06ae88d49246f704dd25330e615fa6b Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 1 Feb 2023 17:04:10 +0100 Subject: [PATCH 4/6] Update registers access on RISCV_OP --- src/simulator/machine.rs | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 45bafe7..d27dc60 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -295,9 +295,9 @@ impl Machine { }, RISCV_OPI_SRI => { if inst.funct7_smaller == RISCV_OPI_SRI_SRLI { - machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64; + machine.int_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1 as usize) >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64); } else { // SRAI - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> inst.shamt; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) >> inst.shamt); } } _ => { panic!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value); } @@ -308,17 +308,17 @@ impl Machine { if inst.funct7 == 1 { match inst.funct3 { RISCV_OP_M_MUL => { - long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; - machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as i64; + long_result = (machine.int_reg.get_reg(inst.rs1 as usize) * machine.int_reg.get_reg(inst.rs2 as usize)) as i128; + machine.int_reg.set_reg(inst.rd as usize, (long_result & 0xffffffffffffffff) as i64); }, RISCV_OP_M_MULH => { - long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; - machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; + long_result = (machine.int_reg.get_reg(inst.rs1 as usize) * machine.int_reg.get_reg(inst.rs2 as usize)) as i128; + machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64); }, RISCV_OP_M_MULHSU => { - unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; - long_result = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128; - machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; + unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64; + long_result = (machine.int_reg.get_reg(inst.rs1 as usize) as u64 * unsigned_reg2) as i128; + machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64); }, // VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve /* @@ -326,13 +326,13 @@ impl Machine { * WHAT DA HECK */ RISCV_OP_M_MULHU => { - unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64; - unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; + unsigned_reg1 = machine.int_reg.get_reg(inst.rs1 as usize) as u64; + unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64; long_result = (unsigned_reg1 * unsigned_reg2) as i128; - machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; + machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64); }, RISCV_OP_M_DIV => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize]; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) / machine.int_reg.get_reg(inst.rs2 as usize)); } _ => { panic!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n"); From 0e89061a031ad6858b1e433164887e19dc396bd9 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 1 Feb 2023 17:10:11 +0100 Subject: [PATCH 5/6] Fix errors preventing compiling --- src/simulator/machine.rs | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 2c6f035..b22d576 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -5,13 +5,13 @@ use super::global::*; /// doit disparaitre const MEM_SIZE : usize = 4096; -trait RegisterNum: Add + Sub + PartialEq + Copy {} +pub trait RegisterNum: Add + Sub + PartialEq + Copy {} impl RegisterNum for i64 {} impl RegisterNum for f32 {} -struct Register { +pub struct Register { register: [U; 32] } @@ -235,16 +235,20 @@ impl Machine { RISCV_LD => { match inst.funct3 { RISCV_LD_LB | RISCV_LD_LBU => { - machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); + let tmp = Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64; + machine.int_reg.set_reg(inst.rd as usize, tmp); }, RISCV_LD_LH | RISCV_LD_LHU => { - machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); + let tmp = Self::read_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64; + machine.int_reg.set_reg(inst.rd as usize, tmp); }, RISCV_LD_LW | RISCV_LD_LWU => { - machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); + let tmp = Self::read_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64; + machine.int_reg.set_reg(inst.rd as usize, tmp); }, RISCV_LD_LD => { - machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); + let tmp = Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64; + machine.int_reg.set_reg(inst.rd as usize, tmp); }, _ => { panic!("In LD switch case, this should never happen... Instr was {}", inst.value); From 658502d3532830bdaeac536b2e88769514761ace Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 1 Feb 2023 17:26:34 +0100 Subject: [PATCH 6/6] Convert some fp reg from array to struct call --- src/simulator/machine.rs | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 913abda..4d4ee63 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -59,6 +59,7 @@ impl Register { pub struct Machine { pub pc : u64, pub int_reg : Register, + pub fp_reg : Register, pub instructions : [u64 ; 100], pub main_memory : [u8 ; MEM_SIZE], pub shiftmask : [u64 ; 64] @@ -86,6 +87,7 @@ impl Machine { pc : 0, instructions : [0 ; 100], int_reg : Register::::init(), + fp_reg: Register::::init(), main_memory : [0 ; MEM_SIZE], shiftmask } @@ -453,19 +455,19 @@ impl Machine { RISCV_FP => { match inst.funct7 { RISCV_FP_ADD => { - machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] + machine.fp_reg[inst.rs2 as usize]; + machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) + machine.fp_reg.get_reg(inst.rs2 as usize)); }, RISCV_FP_SUB => { - machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] - machine.fp_reg[inst.rs2 as usize]; + machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) - machine.fp_reg.get_reg(inst.rs2 as usize)); }, RISCV_FP_MUL => { - machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] * machine.fp_reg[inst.rs2 as usize]; + machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) * machine.fp_reg.get_reg(inst.rs2 as usize)); }, RISCV_FP_DIV => { - machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] / machine.fp_reg[inst.rs2 as usize]; + machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) / machine.fp_reg.get_reg(inst.rs2 as usize)); }, RISCV_FP_SQRT => { - machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize].sqrt(); + machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize).sqrt()); }, RISCV_FP_FSGN => { let local_float = machine.fp_reg[inst.rs1 as usize];