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Merge branch 'delinted_machine_rs' into decode_print

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François Autin 2023-01-11 15:05:46 +01:00
commit f4b6cb3137
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1 changed files with 26 additions and 26 deletions
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52
src/simulator/machine.rs
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@ -21,8 +21,8 @@ impl Machine {
let mut value : u64 = 0xffffffff; let mut value : u64 = 0xffffffff;
value = (value << 32) + value; value = (value << 32) + value;
for i in 0..64 { for item in &mut shiftmask {
shiftmask[i] = value; *item = value;
value = value >> 1; value = value >> 1;
} }
@ -31,7 +31,7 @@ impl Machine {
instructions : [0 ; 100], instructions : [0 ; 100],
int_reg : [0 ; 32], int_reg : [0 ; 32],
main_memory : [0 ; MEM_SIZE], main_memory : [0 ; MEM_SIZE],
shiftmask : shiftmask shiftmask
} }
} }
@ -49,18 +49,18 @@ impl Machine {
let mut ret : u64 = machine.main_memory[address] as u64; let mut ret : u64 = machine.main_memory[address] as u64;
if size == 2 || size == 4 || size == 8 { if size == 2 || size == 4 || size == 8 {
ret = ret << 8; ret <<= 8;
ret += machine.main_memory[address + 1] as u64; ret += machine.main_memory[address + 1] as u64;
} }
if size == 4 || size == 8 { if size == 4 || size == 8 {
ret = ret << 8; ret <<= 8;
ret += machine.main_memory[address + 2] as u64; ret += machine.main_memory[address + 2] as u64;
} }
if size == 8 { if size == 8 {
ret = ret << 8; ret <<= 8;
ret += machine.main_memory[address + 3] as u64; ret += machine.main_memory[address + 3] as u64;
} }
return ret; ret
} }
/// Execute the instructions table of a machine putted in param /// Execute the instructions table of a machine putted in param
@ -82,14 +82,14 @@ impl Machine {
/// - **machine** which contains a table of instructions and a pc to the actual instruction /// - **machine** which contains a table of instructions and a pc to the actual instruction
pub fn one_instruction(machine :&mut Machine) { pub fn one_instruction(machine :&mut Machine) {
let mut unsigned_reg1 : u64 = 0; let unsigned_reg1 : u64;
let mut unsigned_reg2 : u64 = 0; let unsigned_reg2 : u64;
let mut long_result : i128 = 0; let long_result : i128;
/*__int128 longResult; /*__int128 longResult;
int32_t localDataa, localDatab; int32_t local_data_a, local_data_b;
int64_t localLongResult; int64_t localLongResult;
uint32_t localDataaUnsigned, localDatabUnsigned; uint32_t local_data_aUnsigned, local_data_bUnsigned;
int32_t localResult; int32_t localResult;
float localFloat; float localFloat;
uint64_t value;*/ uint64_t value;*/
@ -133,22 +133,22 @@ impl Machine {
machine.pc += inst.imm13_signed as u64 - 4; machine.pc += inst.imm13_signed as u64 - 4;
} }
}, },
RICV_BR_BLT => { RISCV_BR_BLT => {
if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
machine.pc += inst.imm13_signed as u64 - 4; machine.pc += inst.imm13_signed as u64 - 4;
} }
}, },
RICV_BR_BGE => { RISCV_BR_BGE => {
if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] { if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] {
machine.pc += inst.imm13_signed as u64 - 4; machine.pc += inst.imm13_signed as u64 - 4;
} }
}, },
RICV_BR_BLTU => { RISCV_BR_BLTU => {
if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
machine.pc += inst.imm13_signed as u64 - 4; machine.pc += inst.imm13_signed as u64 - 4;
} }
}, },
RICV_BR_BGEU => { RISCV_BR_BGEU => {
if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] { if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] {
machine.pc += inst.imm13_signed as u64 - 4; machine.pc += inst.imm13_signed as u64 - 4;
} }
@ -265,7 +265,7 @@ impl Machine {
} else { } else {
match inst.funct3 { match inst.funct3 {
RISCV_OP_ADD => { RISCV_OP_ADD => {
if (inst.funct7 == RISCV_OP_ADD_ADD) { if inst.funct7 == RISCV_OP_ADD_ADD {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize]; machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];
} else { } else {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize]; machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize];
@ -313,27 +313,27 @@ impl Machine {
// Treatment for: OPW INSTRUCTIONS // Treatment for: OPW INSTRUCTIONS
RISCV_OPW => { RISCV_OPW => {
if inst.funct7 == 1 { if inst.funct7 == 1 {
let localDataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff; let local_data_a = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
let localDatab = machine.int_reg[inst.rs2 as usize] & 0xffffffff; let local_data_b = machine.int_reg[inst.rs2 as usize] & 0xffffffff;
let localDataaUnsigned = machine.int_reg[inst.rs1 as usize] & 0xffffffff; let local_data_a_unsigned = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
let localDatabUnsigned = machine.int_reg[inst.rs2 as usize] & 0xffffffff; let local_data_b_unsigned = machine.int_reg[inst.rs2 as usize] & 0xffffffff;
// Match case for multiplication operations (in standard extension RV32M) // Match case for multiplication operations (in standard extension RV32M)
match inst.funct3 { match inst.funct3 {
RISCV_OPW_M_MULW => { RISCV_OPW_M_MULW => {
machine.int_reg[inst.rd as usize] = localDataa * localDatab; machine.int_reg[inst.rd as usize] = local_data_a * local_data_b;
}, },
RISCV_OPW_M_DIVW => { RISCV_OPW_M_DIVW => {
machine.int_reg[inst.rd as usize] = localDataa / localDatab; machine.int_reg[inst.rd as usize] = local_data_a / local_data_b;
}, },
RISCV_OPW_M_DIVUW => { RISCV_OPW_M_DIVUW => {
machine.int_reg[inst.rd as usize] = localDataaUnsigned / localDatabUnsigned; machine.int_reg[inst.rd as usize] = local_data_a_unsigned / local_data_b_unsigned;
}, },
RISCV_OPW_M_REMW => { RISCV_OPW_M_REMW => {
machine.int_reg[inst.rd as usize] = localDataa % localDatab; machine.int_reg[inst.rd as usize] = local_data_a % local_data_b;
}, },
RISCV_OPW_M_REMUW => { RISCV_OPW_M_REMUW => {
machine.int_reg[inst.rd as usize] = localDataaUnsigned % localDatabUnsigned; machine.int_reg[inst.rd as usize] = local_data_a_unsigned % local_data_b_unsigned;
}, },
_ => { _ => {
println!("this instruction ({}) doesn't exists", inst.value); println!("this instruction ({}) doesn't exists", inst.value);