add floating point instructions
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40374bf26f
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@ -398,6 +398,114 @@ impl Machine {
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//******************************************************************************************
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// Treatment for: Simple floating point extension
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RISCV_FP => {
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match inst.funct7 {
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RISCV_FP_ADD => {
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machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] + machine.fp_reg[inst.rs2 as usize];
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},
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RISCV_FP_SUB => {
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machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] - machine.fp_reg[inst.rs2 as usize];
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},
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RISCV_FP_MUL => {
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machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] * machine.fp_reg[inst.rs2 as usize];
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},
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RISCV_FP_DIV => {
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machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] / machine.fp_reg[inst.rs2 as usize];
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},
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RISCV_FP_SQRT => {
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machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize].sqrt();
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},
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RISCV_FP_FSGN => {
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let local_float = machine.fp_reg[inst.rs1 as usize];
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match inst.funct3 {
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RISCV_FP_FSGN_J => {
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if machine.fp_reg[inst.rs2 as usize] < 0 {
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machine.fp_reg[inst.rd as usize] = -local_float;
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} else {
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machine.fp_reg[inst.rd as usize] = local_float;
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}
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}
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RISCV_FP_FSGN_JN => {
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if machine.fp_reg[inst.rs2 as usize] < 0 {
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machine.fp_reg[inst.rd as usize] = local_float;
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} else {
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machine.fp_reg[inst.rd as usize] = -local_float;
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}
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}
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RISCV_FP_FSGN_JX => {
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if (machine.fp_reg[inst.rs2 as usize] < 0 && machine.fp_reg[inst.rs1 as usize] >= 0) || (machine.fp_reg[inst.rs2 as usize] >= 0 && machine.fp_reg[inst.rs1 as usize] < 0) {
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machine.fp_reg[inst.rd as usize] = -local_float;
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} else {
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machine.fp_reg[inst.rd as usize] = local_float;
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}
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}
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_ => {
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panic!("this instruction ({}) doesn't exists", inst.value);
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}
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}
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},
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RISCV_FP_MINMAX => {
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let r1 = machine.fp_reg[inst.rs1 as usize];
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let r2 = machine.fp_reg[inst.rs2 as usize];
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match inst.funct3 {
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RISCV_FP_MINMAX_MIN => {
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machine.fp_reg[inst.rd as usize] = if r1 < r2 {r1} else {r2}
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},
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RISCV_FP_MINMAX_MAX => {
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machine.fp_reg[inst.rd as usize] = if r1 > r2 {r1} else {r2}
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},
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_ => {
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panic!("this instruction ({}) doesn't exists", inst.value);
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}
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}
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},
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RISCV_FP_FCVTW => {
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if inst.rs2 == RISCV_FP_FCVTW_W {
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machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize];
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} else {
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machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] as u64;
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}
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},
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RISCV_FP_FCVTS => {
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if inst.rs2 == RISCV_FP_FCVTS_W {
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machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize];
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} else {
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machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] as u32;
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}
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},
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RISCV_FP_FMVW => {
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machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize];
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},
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RISCV_FP_FMVXFCLASS => {
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if inst.funct3 == RISCV_FP_FMVXFCLASS_FMVX {
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machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize];
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} else {
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panic!("Fclass instruction is not handled in riscv simulator");
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}
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},
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RISCV_FP_FCMP => {
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match inst.funct3 {
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RISCV_FP_FCMP_FEQ => {
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machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] == machine.fp_reg[inst.rs2 as usize] {1} else {0};
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},
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RISCV_FP_FCMP_FLT => {
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machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] < machine.fp_reg[inst.rs2 as usize] {1} else {0};
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},
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RISCV_FP_FCMP_FLE => {
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machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] <= machine.fp_reg[inst.rs2 as usize] {1} else {0};
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},
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_ => {
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panic!("this instruction ({}) doesn't exists", inst.value);
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}
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}
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},
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_ => {
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panic!("this instruction ({}) doesn't exists", inst.value);
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}
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}
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}
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}
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_ => { panic!("{} opcode non géré", inst.opcode)},
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_ => { panic!("{} opcode non géré", inst.opcode)},
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}
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}
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