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impl register for floating point (from bottom)

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Baptiste 2023-02-01 17:29:31 +01:00
parent d04072c89a
commit 1c6606eb35
1 changed files with 18 additions and 16 deletions
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34
src/simulator/machine.rs
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@ -59,6 +59,7 @@ impl Register<f32> {
pub struct Machine { pub struct Machine {
pub pc : u64, pub pc : u64,
pub int_reg : Register<i64>, pub int_reg : Register<i64>,
pub fp_reg : Register<f32>,
pub instructions : [u64 ; 100], pub instructions : [u64 ; 100],
pub main_memory : [u8 ; MEM_SIZE], pub main_memory : [u8 ; MEM_SIZE],
pub shiftmask : [u64 ; 64] pub shiftmask : [u64 ; 64]
@ -86,6 +87,7 @@ impl Machine {
pc : 0, pc : 0,
instructions : [0 ; 100], instructions : [0 ; 100],
int_reg : Register::<i64>::init(), int_reg : Register::<i64>::init(),
fp_reg : Register::<f32>::init(),
main_memory : [0 ; MEM_SIZE], main_memory : [0 ; MEM_SIZE],
shiftmask shiftmask
} }
@ -485,10 +487,10 @@ impl Machine {
} }
} }
RISCV_FP_FSGN_JX => { RISCV_FP_FSGN_JX => {
if (machine.fp_reg[inst.rs2 as usize] < 0 && machine.fp_reg[inst.rs1 as usize] >= 0) || (machine.fp_reg[inst.rs2 as usize] >= 0 && machine.fp_reg[inst.rs1 as usize] < 0) { if (machine.fp_reg.get_reg(inst.rs2 as usize) < 0.0 && machine.fp_reg.get_reg(inst.rs1 as usize) >= 0.0) || (machine.fp_reg.get_reg(inst.rs2 as usize) >= 0.0 && machine.fp_reg.get_reg(inst.rs1 as usize) < 0.0) {
machine.fp_reg[inst.rd as usize] = -local_float; machine.fp_reg.set_reg(inst.rd as usize, -local_float);
} else { } else {
machine.fp_reg[inst.rd as usize] = local_float; machine.fp_reg.set_reg(inst.rd as usize, local_float);
} }
} }
_ => { _ => {
@ -497,14 +499,14 @@ impl Machine {
} }
}, },
RISCV_FP_MINMAX => { RISCV_FP_MINMAX => {
let r1 = machine.fp_reg[inst.rs1 as usize]; let r1 = machine.fp_reg.get_reg(inst.rs1 as usize);
let r2 = machine.fp_reg[inst.rs2 as usize]; let r2 = machine.fp_reg.get_reg(inst.rs2 as usize);
match inst.funct3 { match inst.funct3 {
RISCV_FP_MINMAX_MIN => { RISCV_FP_MINMAX_MIN => {
machine.fp_reg[inst.rd as usize] = if r1 < r2 {r1} else {r2} machine.fp_reg.set_reg(inst.rd as usize, if r1 < r2 {r1} else {r2});
}, },
RISCV_FP_MINMAX_MAX => { RISCV_FP_MINMAX_MAX => {
machine.fp_reg[inst.rd as usize] = if r1 > r2 {r1} else {r2} machine.fp_reg.set_reg(inst.rd as usize, if r1 > r2 {r1} else {r2});
}, },
_ => { _ => {
panic!("this instruction ({}) doesn't exists", inst.value); panic!("this instruction ({}) doesn't exists", inst.value);
@ -513,24 +515,24 @@ impl Machine {
}, },
RISCV_FP_FCVTW => { RISCV_FP_FCVTW => {
if inst.rs2 == RISCV_FP_FCVTW_W { if inst.rs2 == RISCV_FP_FCVTW_W {
machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize]; machine.int_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) as i64);
} else { } else {
machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] as u64; machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1 as usize) as u64) as i64);
} }
}, },
RISCV_FP_FCVTS => { RISCV_FP_FCVTS => {
if inst.rs2 == RISCV_FP_FCVTS_W { if inst.rs2 == RISCV_FP_FCVTS_W {
machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize]; machine.fp_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) as f32);
} else { } else {
machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] as u32; machine.fp_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1 as usize) as u32) as f32);
} }
}, },
RISCV_FP_FMVW => { RISCV_FP_FMVW => {
machine.fp_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize]; machine.fp_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) as f32);
}, },
RISCV_FP_FMVXFCLASS => { RISCV_FP_FMVXFCLASS => {
if inst.funct3 == RISCV_FP_FMVXFCLASS_FMVX { if inst.funct3 == RISCV_FP_FMVXFCLASS_FMVX {
machine.int_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize]; machine.int_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) as i64);
} else { } else {
panic!("Fclass instruction is not handled in riscv simulator"); panic!("Fclass instruction is not handled in riscv simulator");
} }
@ -538,13 +540,13 @@ impl Machine {
RISCV_FP_FCMP => { RISCV_FP_FCMP => {
match inst.funct3 { match inst.funct3 {
RISCV_FP_FCMP_FEQ => { RISCV_FP_FCMP_FEQ => {
machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] == machine.fp_reg[inst.rs2 as usize] {1} else {0}; machine.int_reg.set_reg(inst.rd as usize, if machine.fp_reg.get_reg(inst.rs1 as usize) == machine.fp_reg.get_reg(inst.rs2 as usize) {1} else {0});
}, },
RISCV_FP_FCMP_FLT => { RISCV_FP_FCMP_FLT => {
machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] < machine.fp_reg[inst.rs2 as usize] {1} else {0}; machine.int_reg.set_reg(inst.rd as usize, if machine.fp_reg.get_reg(inst.rs1 as usize) < machine.fp_reg.get_reg(inst.rs2 as usize) {1} else {0});
}, },
RISCV_FP_FCMP_FLE => { RISCV_FP_FCMP_FLE => {
machine.int_reg[inst.rd as usize] = if machine.fp_reg[inst.rs1 as usize] <= machine.fp_reg[inst.rs2 as usize] {1} else {0}; machine.int_reg.set_reg(inst.rd as usize, if machine.fp_reg.get_reg(inst.rs1 as usize) <= machine.fp_reg.get_reg(inst.rs2 as usize) {1} else {0});
}, },
_ => { _ => {
panic!("this instruction ({}) doesn't exists", inst.value); panic!("this instruction ({}) doesn't exists", inst.value);