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simulate some instructions

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This commit is contained in:
Baptiste 2022-11-09 17:35:16 +01:00
parent c5291b7a3b
commit 240f029881
2 changed files with 31 additions and 7 deletions
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30
src/machine.rs
View File

@ -1,5 +1,3 @@
#[warn(unused_parens)]
use crate::decode::*;
use crate::print::*;
@ -26,12 +24,40 @@ impl Machine {
println!("ERROR : number max of instructions rushed");
return machine;
}
let inst : Instruction = decode(machine.instructions[machine.pc as usize]);
machine.pc += 1;
match (inst.opcode) {
RISCV_LUI => {
machine.int_reg[inst.rd as usize] = inst.imm31_12;
},
//******************************************************************************************
// Treatment for: OPI INSTRUCTIONS
RISCV_OPI => {
match (inst.funct3) {
RISCV_OPI_ADDI => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as u32;
},
RISCV_OPI_SLTI => {
machine.int_reg[inst.rd as usize] =
if machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as u32 { 1 } else { 0 };
},
RISCV_OPI_XORI => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as u32;
},
RISCV_OPI_ORI => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | inst.imm12_I_signed as u32;
},
RISCV_OPI_ANDI => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & inst.imm12_I_signed as u32;
},
RISCV_OPI_SLLI => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt;
}
}
},
}

8
src/main.rs
View File

@ -1,12 +1,10 @@
mod decode;
mod print;
mod machine;
use machine::Machine;
fn main() {
let instr = decode::decode(98);
println!("{}", print::print(instr, 0));
let mut m = machine::Machine::_init_machine();
let mut m = Machine::_init_machine();
m.instructions[0] = 0x37;
machine::Machine::oneInstruction(m);
Machine::oneInstruction(m);
}