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fix ADD_ADD

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This commit is contained in:
Baptiste 2022-12-07 17:09:53 +01:00
parent 4fa691a568
commit 27cd7d35c7
1 changed files with 9 additions and 7 deletions
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12
src/machine.rs
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@ -102,7 +102,6 @@ impl Machine {
let inst : Instruction = decode(machine.instructions[machine.pc as usize]); let inst : Instruction = decode(machine.instructions[machine.pc as usize]);
machine.pc += 4;
match inst.opcode { match inst.opcode {
RISCV_LUI => { RISCV_LUI => {
@ -194,6 +193,8 @@ impl Machine {
} }
}, },
//TODO store instructions
//****************************************************************************************** //******************************************************************************************
// Treatment for: OPI INSTRUCTIONS // Treatment for: OPI INSTRUCTIONS
RISCV_OPI => { RISCV_OPI => {
@ -265,11 +266,11 @@ impl Machine {
} else { } else {
match inst.funct3 { match inst.funct3 {
RISCV_OP_ADD => { RISCV_OP_ADD => {
// RISCV_OP_ADD_ADD inaccessible if (inst.funct7 == RISCV_OP_ADD_ADD) {
/*if (inst.funct7 == RISCV_OP_ADD_ADD) { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];*/ } else {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize]; machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize];
//} }
}, },
RISCV_OP_SLL => { RISCV_OP_SLL => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f); machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f);
@ -371,6 +372,7 @@ impl Machine {
_ => { println!("{} opcode non géré", inst.opcode)}, _ => { println!("{} opcode non géré", inst.opcode)},
} }
machine.pc += 4;
} }
} }