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RISCV_OP fixed

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This commit is contained in:
Samy Solhi 2022-11-09 14:37:19 +01:00
parent 673c2c8d20
commit 7a89d06f36
1 changed files with 17 additions and 1 deletions
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18
src/print.rs
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@ -147,7 +147,23 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
if ins.funct7 == 1 { // Use mul array
name = names_mul[ins.funct3 as usize]
} else {
name = names_op[ins.funct3 as usize];
if ins.funct3 == RISCV_OP_ADD {
// Add or Sub
if ins.funct7 == RISCV_OP_ADD_ADD {
name = "add";
} else {
name = "sub";
}
} else if ins.funct3 == RISCV_OP_SR {
// Srl or Sra
if ins.funct7 == RISCV_OP_SR_SRL {
name = "srl";
} else {
name = "sra";
}
} else {
name = names_op[ins.funct3 as usize];
}
}
format!("{} r{}, r{}, r{}", name.to_string(), &ins.rd.to_string(), &ins.rs1.to_string(), &ins.rs2.to_string())
},