Merge branch 'decode_print' of gitlab.istic.univ-rennes1.fr:simpleos/burritos into decode_print
This commit is contained in:
Aelbahri
commit
b6d494781e
@ -23,7 +23,7 @@ impl Machine {
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value = (value << 32) + value;
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for item in &mut shiftmask {
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*item = value;
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value = value >> 1;
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value >>= 1;
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}
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Machine {
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@ -44,7 +44,7 @@ impl Machine {
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/// - **address** in the memory to read
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pub fn read_memory(machine : &mut Machine, size : i32, address : usize) -> u64 {
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if size != 1 && size != 2 && size != 4 && size != 8 {
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println!("ERROR read_memory : wrong size parameter {}, must be (1, 2, 4 or 8)", size);
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panic!("ERROR read_memory : wrong size parameter {}, must be (1, 2, 4 or 8)", size);
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}
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let mut ret : u64 = machine.main_memory[address] as u64;
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@ -202,8 +202,7 @@ impl Machine {
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machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64;
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},
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RISCV_OPI_SLTI => {
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machine.int_reg[inst.rd as usize] =
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if machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as i64 { 1 } else { 0 };
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machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as i64) as i64;
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},
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RISCV_OPI_XORI => {
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machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as i64;
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@ -378,6 +377,5 @@ impl Machine {
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#[cfg(test)]
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mod test {
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use super::Machine;
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}
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}
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@ -163,22 +163,22 @@ pub const RISCV_ATOM_MINU: u8 = 0x18;
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pub const RISCV_ATOM_MAXU: u8 = 0x1c;
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const names_op: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"];
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const names_opi: [&str; 8] = ["addi", "slli", "slti", "sltiu", "xori", "slri", "ori", "andi"];
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const names_mul: [&str; 8] = ["mpylo", "mpyhi", "mpyhi", "mpyhi", "divhi", "divhi", "divlo", "divlo"];
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const names_br: [&str; 8] = ["beq", "bne", "", "", "blt", "bge", "bltu", "bgeu"];
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const names_st: [&str; 4] = ["sb", "sh", "sw", "sd"];
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const names_ld: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"];
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const names_opw: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""];
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const names_opiw: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""];
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const NAMES_OP: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"];
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const NAMES_OPI: [&str; 8] = ["addi", "slli", "slti", "sltiu", "xori", "slri", "ori", "andi"];
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const NAMES_MUL: [&str; 8] = ["mpylo", "mpyhi", "mpyhi", "mpyhi", "divhi", "divhi", "divlo", "divlo"];
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const NAMES_BR: [&str; 8] = ["beq", "bne", "", "", "blt", "bge", "bltu", "bgeu"];
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const NAMES_ST: [&str; 4] = ["sb", "sh", "sw", "sd"];
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const NAMES_LD: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"];
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const NAMES_OPW: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""];
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const NAMES_OPIW: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""];
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// Register name mapping
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const reg_x: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1", // fp ou s0 ?
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const REG_X: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1", // fp ou s0 ?
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"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
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"s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
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"t3", "t4", "t5", "t6"];
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const _reg_f: [&str; 32] = ["ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1",
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const REG_F: [&str; 32] = ["ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1",
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"fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7",
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"fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11",
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"ft8", "ft9", "ft10", "ft11"];
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@ -193,53 +193,51 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
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RISCV_OP => {
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let name: &str;
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if ins.funct7 == 1 { // Use mul array
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name = names_mul[ins.funct3 as usize]
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} else {
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if ins.funct3 == RISCV_OP_ADD {
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// Add or Sub
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if ins.funct7 == RISCV_OP_ADD_ADD {
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name = "add";
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} else {
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name = "sub";
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}
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} else if ins.funct3 == RISCV_OP_SR {
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// Srl or Sra
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if ins.funct7 == RISCV_OP_SR_SRL {
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name = "srl";
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} else {
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name = "sra";
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}
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name = NAMES_MUL[ins.funct3 as usize]
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} else if ins.funct3 == RISCV_OP_ADD {
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// Add or Sub
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if ins.funct7 == RISCV_OP_ADD_ADD {
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name = "add";
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} else {
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name = names_op[ins.funct3 as usize];
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name = "sub";
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}
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} else if ins.funct3 == RISCV_OP_SR {
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// Srl or Sra
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if ins.funct7 == RISCV_OP_SR_SRL {
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name = "srl";
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} else {
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name = "sra";
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}
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} else {
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name = NAMES_OP[ins.funct3 as usize];
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}
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format!("{}\t{}, {}, {}", name.to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2])
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format!("{}\t{}, {}, {}", name, REG_X[rd], REG_X[rs1], REG_X[rs2])
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},
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RISCV_OPI => {
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// SHAMT OR IMM
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if ins.funct3 == RISCV_OPI_SRI {
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if ins.funct7 == RISCV_OPI_SRI_SRLI {
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format!("slrii\t{}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string())
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format!("slrii\t{}, {}, {}", REG_X[rd], REG_X[rs1], ins.shamt)
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} else {
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format!("srai\t{}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string())
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format!("srai\t{}, {}, {}", REG_X[rd], REG_X[rs1], ins.shamt)
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}
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} else if ins.funct3 == RISCV_OPI_SLLI {
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format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.shamt.to_string())
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format!("{}\t{}, {}, {}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.shamt)
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} else {
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format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string())
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format!("{}\t{}, {}, {}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed)
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}
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},
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RISCV_LUI => {
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format!("lui\t{}, 0x{:X}", reg_x[rd], ins.imm31_12)
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format!("lui\t{}, 0x{:X}", REG_X[rd], ins.imm31_12)
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},
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RISCV_AUIPC => {
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format!("auipc\t{}, {:X}", reg_x[rd], ins.imm31_12)
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format!("auipc\t{}, {:X}", REG_X[rd], ins.imm31_12)
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},
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RISCV_JAL => {
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if ins.rd == 0 {
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format!("j\t{}", ins.imm31_12.to_string())
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format!("j\t{}", ins.imm31_12)
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} else {
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format!("jal\t{}, {:X}", reg_x[rd], (pc - 4 + ins.imm21_1_signed))
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format!("jal\t{}, {:X}", REG_X[rd], (pc - 4 + ins.imm21_1_signed))
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}
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},
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RISCV_JALR => {
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@ -250,50 +248,48 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
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format!("jr\t{:X}", ins.imm31_12)
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}
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} else {
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format!("jalr\t{}, ({})", ins.imm12_I_signed.to_string(), reg_x[rs1])
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format!("jalr\t{}, ({})", ins.imm12_I_signed, REG_X[rs1])
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}
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},
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RISCV_BR => {
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format!("{}\t{}, {}, {}", names_br[ins.funct3 as usize].to_string(), reg_x[rs1], reg_x[rs2], ins.imm13_signed.to_string())
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format!("{}\t{}, {}, {}", NAMES_BR[ins.funct3 as usize], REG_X[rs1], REG_X[rs2], ins.imm13_signed)
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},
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RISCV_LD => {
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format!("{}\t{}, {}({})", names_ld[ins.funct3 as usize].to_string(), reg_x[rd], ins.imm12_I_signed.to_string(), reg_x[rs1])
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format!("{}\t{}, {}({})", NAMES_LD[ins.funct3 as usize], REG_X[rd], ins.imm12_I_signed, REG_X[rs1])
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},
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RISCV_ST => {
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format!("{}\t{}, {}({})", names_st[ins.funct3 as usize].to_string(), reg_x[rs2], ins.imm12_S_signed.to_string(), reg_x[rs1])
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format!("{}\t{}, {}({})", NAMES_ST[ins.funct3 as usize], REG_X[rs2], ins.imm12_S_signed, REG_X[rs1])
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},
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RISCV_OPIW => {
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if ins.funct3 == RISCV_OPIW_SRW {
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if ins.funct7 == RISCV_OPIW_SRW_SRLIW {
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format!("srlwi\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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format!("srlwi\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2])
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} else {
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format!("srawi\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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format!("srawi\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2])
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}
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} else if ins.funct3 == RISCV_OPIW_SLLIW {
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format!("{}\t{}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2])
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format!("{}\t{}, {}, {}", NAMES_OPI[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2])
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} else {
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format!("{}\t{}, {}, {}", names_opiw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string())
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format!("{}\t{}, {}, {}", NAMES_OPIW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], ins.imm12_I_signed)
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}
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},
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RISCV_OPW => {
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if ins.funct7 == 1 {
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format!("{}w\t{}, {}, {}", names_mul[ins.funct3 as usize].to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2])
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} else {
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if ins.funct3 == RISCV_OP_ADD {
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if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW {
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format!("addw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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} else {
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format!("subw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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}
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} else if ins.funct3 == RISCV_OPW_SRW {
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if ins.funct7 == RISCV_OPW_SRW_SRLW {
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format!("srlw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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} else {
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format!("sraw\t{}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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}
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format!("{}w\t{}, {}, {}", NAMES_MUL[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2])
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} else if ins.funct3 == RISCV_OP_ADD {
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if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW {
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format!("addw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2])
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} else {
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format!("{}\t{}, {}, {}", names_opw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2])
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format!("subw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2])
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}
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} else if ins.funct3 == RISCV_OPW_SRW {
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if ins.funct7 == RISCV_OPW_SRW_SRLW {
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format!("srlw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2])
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} else {
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format!("sraw\t{}, {}, {}", REG_X[rd], REG_X[rs1], REG_X[rs2])
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}
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} else {
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format!("{}\t{}, {}, {}", NAMES_OPW[ins.funct3 as usize], REG_X[rd], REG_X[rs1], REG_X[rs2])
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}
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},
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RISCV_SYSTEM => {
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@ -307,6 +303,8 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
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#[cfg(test)]
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mod test {
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#![allow(clippy::unusual_byte_groupings)]
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use crate::simulator::{decode, print};
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